PIC17C756-16/L Microchip Technology, PIC17C756-16/L Datasheet - Page 228
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC17C756-16/L
Manufacturer Part Number
PIC17C756-16/L
Description
MICRO CTRL 16K MEMORY OTP 68PLCC
Manufacturer
Microchip Technology
Series
PIC® 17Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC17C752-16L.pdf
(304 pages)
3.PIC17C752-16L.pdf
(4 pages)
4.PIC17C752-16L.pdf
(6 pages)
5.PIC17C756CL.pdf
(321 pages)
Specifications of PIC17C756-16/L
Core Processor
PIC
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
50
Program Memory Size
32KB (16K x 16)
Program Memory Type
OTP
Ram Size
902 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 6 V
Data Converters
A/D 12x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
For Use With
AC164308 - MODULE SKT FOR PM3 68PLCCDVA17XL681 - DEVICE ADAPTER FOR PIC17C752DM173001 - KIT DEVELOPMENT PICDEM17AC174007 - MODULE SKT PROMATEII 68PLCCAC164024 - ADAPTER PICSTART PLUS 68PLCC
Lead Free Status / RoHS Status
Request inventory verification / Request inventory verification
Eeprom Size
-
- PIC16F616T-ISL PDF datasheet
- PIC17C752-16L PDF datasheet #2
- PIC17C752-16L PDF datasheet #3
- PIC17C752-16L PDF datasheet #4
- PIC17C756CL PDF datasheet #5
- Current page: 228 of 304
- Download datasheet (6Mb)
PIC17C7XX
TABLRD
Example1:
Example2:
DS30289B-page 228
Before Instruction
After Instruction (table write completion)
Before Instruction
After Instruction (table write completion)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
REG
TBLATH
TBLATL
TBLPTR
MEMORY(TBLPTR)
Table Read
TABLRD
TABLRD
1, 1, REG ;
0, 0, REG ;
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
0x53
0xAA
0x55
0xA356
0x1234
0xAA
0x12
0x34
0xA357
0x5678
0x53
0xAA
0x55
0xA356
0x1234
0x55
0x12
0x34
0xA356
0x1234
TABLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Note:
operation
Decode
Q1
No
The MCLR/V
voltage for successful programming of internal
memory.
If MCLR/V
the programming sequence of internal memory
will be interrupted. A short write will occur (2
T
affected.
CY
). The internal memory location will not be
(Table Pointer
on Address
register 'f'
operation
Table Write
[ label ] TABLWT t,i,f
0
i
t
If t = 0,
f
If t = 1,
f
TBLAT
If i = 1,
TBLPTR + 1
If i = 0,
TBLPTR is unchanged
None
1.
2.
3.
1
2 (many if write is to on-chip
EPROM program memory)
Read
bus)
PP
Q2
No
1010
[0,1]
[0,1]
PP
f
= V
TBLATL;
TBLATH;
Load value in ’f’ into 16-bit table
latch (TBLAT)
If t = 1: load into high byte;
If t = 0: load into low byte
The contents of TBLAT are writ-
ten to the program memory
location pointed to by TBLPTR.
If TBLPTR points to external
program memory location, then
the instruction takes two-cycle.
If TBLPTR points to an internal
EPROM
instruction is terminated when
an interrupt is received.
The TBLPTR can be automati-
cally incremented
If i = 1; TBLPTR is not
If i = 0; TBLPTR is incremented
pin must be at the programming
2000 Microchip Technology Inc.
255
DD
Prog Mem (TBLPTR);
11ti
operation
Process
incremented
Data
Q3
No
location,
TBLPTR
ffff
(Table Latch on
WR goes low)
Address bus,
TBLATH or
operation
then
TBLATL
register
Write
Q4
No
ffff
the
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