AT90LS2323-4SI Atmel, AT90LS2323-4SI Datasheet - Page 24

• Manufacturer Part Number: AT90LS2323-4SI
• Description: IC MCU 2K FLASH 4MHZ LV 8-SOIC
• Manufacturer: Atmel
• Series: AVR® 90LSr

Specifications of AT90LS2323-4SI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 3
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -

Interrupt Handling
General Interrupt Mask
Register – GIMSK
24
AT90S/LS2323/2343
Table 8. Reset Source Identification
The AT90S2323/2343 has two 8-bit interrupt mask control registers; GIMSK (General
Interrupt Mask register) and TIMSK (Timer/Counter Interrupt Mask register).
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-
rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.
The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.
When the Program Counter is vectored to the actual interrupt vector in order to execute
the interrupt handling routine, hardware clears the corresponding flag that generated the
interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the
flag bit position(s) to be cleared. If an interrupt condition occurs when the corresponding
interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until
the interrupt is enabled or the flag is cleared by software.
If one or more interrupt conditions occur when the global interrupt enable bit is cleared
(zero), the corresponding interrupt flag(s) will be set and remembered until the global
interrupt enable bit is set (one) and will be executed by order of priority.
Note that external level interrupt does not have a flag and will only be remembered for
as long as the interrupt condition is active.
Note that the Status Register is not automatically stored when entering an interrupt rou-
tine and restored when returning from an interrupt routine. This must be handled by
software.
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the AT90S2323/2343 and always reads as zero.
• Bit 6 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),
the external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and
ISC00) in the MCU general Control Register (MCUCR) define whether the external
interrupt is activated on rising or falling edge of the INT0 pin or level sensed. Activity on
the pin will cause an interrupt request even if INT0 is configured as an output. The corre-
sponding interrupt of External Interrupt Request 0 is executed from program memory
address $001. See also “External Interrupts.”
• Bits 5..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S2323/2343 and always read as zero.
Bit
$3B ($5B)
Read/Write
Initial Value
PORF
0
0
1
1
R
7
–
0
INT0
R/W
6
0
EXTRF
R
5
–
0
0
1
0
1
R
4
–
0
Reset Source
Watchdog Reset
External Reset
Power-on Reset
Power-on Reset
R
3
–
0
R
2
–
0
R
1
–
0
R
0
–
0
1004D–09/01
GIMSK