AT90S2313-4PC Atmel, AT90S2313-4PC Datasheet - Page 26

• Manufacturer Part Number: AT90S2313-4PC
• Description: IC MCU 2K 4MHZ UART LV 20DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2313-4PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Lead Free Status / Rohs Status: No

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AT90S2313
• Bit 4 – SM: Sleep Mode
This bit selects between the two available sleep modes. When SM is cleared (zero), Idle
mode is selected as sleep mode. When SM is set (one), Power-down mode is selected
as sleep mode. For details, refer to the paragraph “Sleep Modes”.
• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the
corresponding interrupt mask in the GIMSK Register is set. The level and edges on the
external INT1 pin that activate the interrupt are defined in Table 5.
Table 5. Interrupt 1 Sense Control
• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the
corresponding interrupt mask is set. The level and edges on the external INT0 pin that
activate the interrupt are defined in Table 6.
Table 6. Interrupt 0 Sense Control
The value on the INTn pin is sampled before detecting edges. If edge interrupt is
selected, pulses with a duration longer than one CPU clock period will generate an inter-
rupt. Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is
selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate
an interrupt request as long as the pin is held low.
ISC11
ISC01
0
0
1
1
0
0
1
1
ISC10
ISC00
0
1
0
1
0
1
0
1
Description
The low level of INT1 generates an interrupt request.
Reserved
The falling edge of INT1 generates an interrupt request.
The rising edge of INT1 generates an interrupt request.
Description
The low level of INT0 generates an interrupt request.
Reserved
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
0839I–AVR–06/02