AT90S2313-4PC Atmel, AT90S2313-4PC Datasheet - Page 46

• Manufacturer Part Number: AT90S2313-4PC
• Description: IC MCU 2K 4MHZ UART LV 20DIP
• Manufacturer: Atmel
• Series: AVR® 90Sr

Specifications of AT90S2313-4PC

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 15
• Program Memory Size: 2KB (1K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-DIP (0.300", 7.62mm)
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI, UART
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 15
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2.7 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Lead Free Status / Rohs Status: No

UART Control Register – UCR
46
AT90S2313
• Bit 4 – FE: Framing Error
This bit is set if a Framing Error condition is detected (i.e., when the stop bit of an incom-
ing character is zero).
The FE bit is cleared when the stop bit of received data is one.
• Bit 3 – OR: OverRun
This bit is set if an OverRun condition is detected (i.e., when a character already present
in the UDR Register is not read before the next character has been shifted into the
Receiver Shift Register). The OR bit is buffered, which means that it will be set once the
valid data still in UDRE is read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
• Bits 2..0 – Res: Reserved Bits
These bits are reserved bits in the AT90S2313 and will always read as zero.
• Bit 7 – RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in USR will cause the Receive Com-
plete Interrupt routine to be executed provided that global interrupts are enabled.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in USR will cause the Transmit Com-
plete Interrupt routine to be executed provided that global interrupts are enabled.
• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDRE bit in USR will cause the UART Data
Register Empty Interrupt routine to be executed provided that global interrupts are
enabled.
• Bit 4 – RXEN: Receiver Enable
This bit enables the UART Receiver when set (one). When the Receiver is disabled, the
RXC, OR and FE Status Flags cannot become set. If these flags are set, turning off
RXEN does not cause them to be cleared.
• Bit 3 – TXEN: Transmitter Enable
This bit enables the UART Transmitter when set (one). When disabling the Transmitter
while transmitting a character, the Transmitter is not disabled before the character in the
Shift Register plus any following character in UDR has been completely transmitted.
• Bit 2 – CHR9: 9 Bit Characters
When this bit is set (one), transmitted and received characters are nine bits long plus
start and stop bits. The ninth bit is read and written by using the RXB8 and TXB8 bits in
UCR, respectively. The ninth data bit can be used as an extra stop bit or a parity bit.
Bit
$0A ($2A)
Read/Write
Initial value
RXCIE
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
CHR9
R/W
2
0
RXB8
R
1
1
TXB8
W
0
0
0839I–AVR–06/02
UCR