AT90LS4433-4AI Atmel, AT90LS4433-4AI Datasheet - Page 58
![IC MCU 4K 4MHZ A/D LV 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
AT90LS4433-4AI
Manufacturer Part Number
AT90LS4433-4AI
Description
IC MCU 4K 4MHZ A/D LV 32TQFP
Manufacturer
Atmel
Series
AVR® 90LSr
Datasheet
1.AT90S4433-8AC.pdf
(126 pages)
Specifications of AT90LS4433-4AI
Core Processor
AVR
Core Size
8-Bit
Speed
4MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 6 V
Data Converters
A/D 6x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90LS4433-4AI
Manufacturer:
HYNIX
Quantity:
14
Part Number:
AT90LS4433-4AI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
UART Control and Status
Register B – UCSRB
58
AT90S/LS4433
• Bit 4 – FE: Framing Error
This bit is set if a Framing Error condition is detected, i.e., when the stop bit of an incom-
ing character is zero.
The FE bit is cleared when the stop bit of received data is one.
• Bit 3 – OR: OverRun
This bit is set if an OverRun condition is detected, i.e., when a character already present
in the UDR Register is not read before the next character has been shifted into the
Receiver Shift Register. The OR bit is buffered, which means that it will be set once the
valid data still in UDRE is read.
The OR bit is cleared (zero) when data is received and transferred to UDR.
• Bits 2..1 – Res: Reserved Bits
These bits are reserved bits in the AT90S4433 and will always read as zero.
• Bit 0 – MPCM: Multi-processor Communication Mode
This bit is used to enter Multi-processor Communication mode. The bit is set when the
slave MCU waits for an address byte to be received. When the MCU has been
addressed, the MCU switches off the MPCM bit and starts data reception.
For a detailed description, see “Multi-processor Communication Mode”.
• Bit 7 – RXCIE: RX Complete Interrupt Enable
When this bit is set (one), a setting of the RXC bit in UCSRA will cause the Receive
Complete Interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 6 – TXCIE: TX Complete Interrupt Enable
When this bit is set (one), a setting of the TXC bit in UCSRA will cause the Transmit
Complete Interrupt routine to be executed, provided that global interrupts are enabled.
• Bit 5 – UDRIE: UART Data Register Empty Interrupt Enable
When this bit is set (one), a setting of the UDRE bit in UCSRA will cause the UART Data
Register Empty Interrupt routine to be executed, provided that global interrupts are
enabled.
• Bit 4 – RXEN: Receiver Enable
This bit enables the UART Receiver when set (one). When the Receiver is disabled, the
RXC, OR, and FE status flags cannot become set. If these flags are set, turning off
RXEN does not cause them to be cleared.
Bit
$0A ($2A)
Read/Write
Initial Value
RXCIE
R/W
7
0
TXCIE
R/W
6
0
UDRIE
R/W
5
0
RXEN
R/W
4
0
TXEN
R/W
3
0
CHR9
R/W
2
0
RXB8
R
1
1
TXB8
W
0
0
1042H–AVR–04/03
UCSRB