ATTINY15L-1PC Atmel, ATTINY15L-1PC Datasheet - Page 42
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ATTINY15L-1PC
Manufacturer Part Number
ATTINY15L-1PC
Description
IC AVR MCU 1K FLASH 2.7V 8DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY15L-1PC
Core Processor
AVR
Core Size
8-Bit
Speed
1.6MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Ram Size
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Operation
42
ATtiny15L
Figure 25. Analog-to-Digital Converter Block Schematic
The ADC converts an analog input voltage to a 10-bit digital value through successive
approximation. The minimum value represents GND and the maximum value represents
the selected reference voltage minus 1 LSB.
The voltage reference for the ADC may be selected by writing to the REFS1..0 bits in
ADMUX. V
voltage reference. Optionally, the 2.56V internal voltage reference may be decoupled by
an external capacitor at the AREF pin to improve noise immunity.
The analog input channel and differential gain are selected by writing to the MUX2..0
bits in ADMUX. Any of the four ADC input pins ADC3..0 can be selected as single-
ended inputs to the ADC. ADC2 and ADC3 can be selected as positive and negative
input, respectively, to the differential gain amplifier.
If differential channels are selected, the differential gain stage amplifies the voltage dif-
ference between the selected input pair by the selected gain factor, 1x or 20x, according
to the setting of the MUX2..0 bits in ADMUX. This amplified value then becomes the
analog input to the ADC. If single-ended channels are used, the gain amplifier is
bypassed altogether.
If ADC2 is selected as both the positive and negative input to the differential gain ampli-
fier (ADC2 - ADC2), the remaining offset in the gain stage and conversion circuitry can
be measured directly as the result of the conversion. This figure can be subtracted from
subsequent conversions with the same gain setting to reduce offset error to below 1
LSB.
The ADC can operate in two modes – Single Conversion and Free Running. In Single
Conversion mode, each conversion will have to be initiated by the user. In Free Running
ADC3
ADC2
ADC1
ADC0
AREF
VCC
REFERENCE
INTERNAL
2.56 V
8-BIT DATA BUS
CC
, the AREF pin, or an internal 2.56V reference may be selected as the ADC
INPUT
NEG.
MUX
INPUT
POS.
MUX
ADC MULTIPLEXER
SELECT (ADMUX)
MUX DECODER
+
-
SINGLE ENDED / DIFFERENTIAL SELECTION
GAIN
AMPLIFIER
10-BIT DAC
ADC CTRL. & STATUS
REGISTER (ADCSR)
ADC CONVERSION
PRESCALER
COMPLETE IRQ
CONVERSION LOGIC
SAMPLE & HOLD
COMPARATOR
+
-
9
ADC DATA REGISTER
(ADCH/ADCL)
1187H–AVR–09/07
0