ATTINY28V-1AC Atmel, ATTINY28V-1AC Datasheet
ATTINY28V-1AC
Specifications of ATTINY28V-1AC
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ATTINY28V-1AC Summary of contents
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... PDIP, 32-lead TQFP, and 32-pad MLF • Operating Voltages – 1.8V - 5.5V for the ATtiny28V CC – 2.7V - 5.5V for the ATtiny28L CC • Speed Grades – 1.2 MHz for the ATtiny28V – MHz For the ATtiny28L Pin Configurations PDIP RESET 1 28 PA0 PD0 2 27 ...
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Description Block Diagram ATtiny28L/V 2 The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi- tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves throughputs approaching 1 MIPS per MHz, allowing the ...
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... The device is manufactured using Atmel’s high-density, nonvolatile memory technology. By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective solution to many embedded control applications ...
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Architectural Overview ATtiny28L/V 4 The fast-access register file concept contains 32 x 8-bit general-purpose working regis- ters with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. ...
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ALU – Arithmetic Logic Unit Subroutine and Interrupt Hardware Stack General-purpose Register File 1062F–AVR–07/ ...
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Status Register Status Register – SREG ATtiny28L/V 6 The AVR status register (SREG) at I/O space location $3F is defined as: Bit $ Read/Write R/W R/W R/W Initial Value • Bit ...
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System Clock and Clock Options Internal RC Oscillator Calibrated Internal RC Oscillator Crystal Oscillator External Clock 1062F–AVR–07/06 The device has the following clock source options, selectable by Flash Fuse bits as shown in Table 1. Table 1. Device Clocking Option ...
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External RC Oscillator ATtiny28L/V 8 Figure 6. External Clock Drive Configuration EXTERNAL OSCILLATOR SIGNAL For timing insensitive applications, the external RC configuration shown in Figure 7 can be used. For details on how to choose R and C, see Table ...
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Register Description Oscillator Calibration Register – OSCCAL 1062F–AVR–07/06 Bit $00 CAL7 CAL6 CAL5 Read/Write R/W R/W R/W Initial Value • Bits 7..0 – CAL7..CAL0: Oscillator Calibration Value Writing the calibration byte to this address ...
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Memories I/O Memory ATtiny28L/V 10 The I/O space definition of the ATtiny28 is shown in Table 3. Table 3. ATtiny28 I/O Space Address Hex Name Function $3F SREG Status Register $1B PORTA Data Register, Port A $1A PACR Port A ...
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Program and Data Addressing Modes Register Direct, Single Register Rd Register Indirect Register Direct, Two Registers Rd and Rr 1062F–AVR–07/06 The ATtiny28 AVR RISC microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in ...
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I/O Direct Relative Program Addressing, RJMP and RCALL Constant Addressing Using the LPM Instruction ATtiny28L/V 12 Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). Figure 11. I/O Direct Addressing Operand ...
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Memory Access and Instruction Execution Timing Flash Program Memory 1062F–AVR–07/06 Constant byte address is specified by the Z-register contents. The 15 MSBs select word address (0 - 1K), and LSB selects low byte if cleared (LSB = 0) or high ...
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Sleep Modes Idle Mode Power-down Mode ATtiny28L enter the sleep modes, the SE bit in MCUCS must be set (one) and a SLEEP instruc- tion must be executed. The SM bit in the MCUCS register selects which sleep ...
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System Control and Reset Reset Sources 1062F–AVR–07/06 The ATtiny28 provides three sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POT • External Reset. The MCU is ...
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Power-on Reset ATtiny28L/V 16 Table 5. ATtiny28 Clock Options and Start-up Time CKSEL3..0 Clock Source 1111 External Crystal/Ceramic Resonator 1110 External Crystal/Ceramic Resonator 1101 External Crystal/Ceramic Resonator 1100 External Crystal/Ceramic Resonator 1011 External Crystal/Ceramic Resonator 1010 External Crystal/Ceramic Resonator 1001 ...
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External Reset 1062F–AVR–07/06 activated again, without any delay, when the V Figure 17. If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via an external pull-up resistor. By holding the RESET pin low for ...
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Watchdog Reset ATtiny28L/V 18 Figure 19. External Reset during Operation VCC RESET V RST TIME-OUT INTERNAL RESET When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura- tion. On the falling edge of ...
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Register Description MCU Control and Status Register – MCUCS 1062F–AVR–07/06 The MCU Control and Status Register contains control and status bits for general MCU functions. Bit $07 PLUPB – SE Read/Write R/W R R/W Initial Value 0 ...
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Interrupts Reset and Interrupt Interrupt Handling ATtiny28L/V 20 The ATtiny28 provides five different interrupt sources. These interrupts and the reset vector each have a separate program vector in the program memory space. All the inter- rupts are assigned to individual ...
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Interrupt Response Time External Interrupt Low-level Input Interrupt 1062F–AVR–07/ interrupt condition occurs when the corresponding interrupt enable bit is cleared (zero), the interrupt flag will be set and remembered until the interrupt is enabled or the flag is ...
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Register Description Interrupt Control Register – ICR ATtiny28L/V 22 Bit $06 INT1 INT0 LLIE Read/Write R/W R/W R/W Initial Value • Bit 7 – INT1: External Interrupt Request 1 Enable When the INT1 bit ...
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Interrupt Flag Register – IFR 1062F–AVR–07/06 Table 8. Interrupt 1 Sense Control ISC11 ISC10 Description 0 0 The low level of INT1 generates an interrupt request Any change on INT1 generates an interrupt request The falling ...
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ATtiny28L/V 24 enable bit, INT0 in GIMSK is set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical “1” to ...
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I/O Ports Port A Port A as General Digital I/O Alternate Function of PA2 1062F–AVR–07/06 All AVR ports have true read-modify-write functionality when used as general digital I/O ports. This means that the direction of one port pin can be ...
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Port A Schematics ATtiny28L/V 26 Note that all port pins are synchronized. The synchronization latches are, however, not shown in the figures. Figure 21. Port A Schematic Diagram (Pins PA0, PA1 and PA3) MOS PULL- UP RESET R PAn Q ...
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Port B Port B as General Digital Input All eight pins in Port B have equal functionality when used as digital input pins. Alternate Functions of Port B 1062F–AVR–07/06 Port 8-bit input port. One I/O address location ...
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Port B Schematics ATtiny28L/V 28 • AIN1 – Port B, Bit 1 AIN1, Analog Comparator Negative input. When the on-chip analog comparator is enabled, this pin also serves as the negative input of the comparator. If the analog com- parator ...
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Figure 24. Port B Schematic Diagram (Pin PB2) MOS PULL- UP PB2 RP: READ PORTB PIN Figure 25. PORT B Schematic Diagram (Pins PB3 and PB4) MOS PULL- UP PBn RP: READ PORTB PIN ...
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Port D Port D as General Digital I/O ATtiny28L/V 30 Figure 26. PORT B Schematic Diagram (Pins PB7 - PB5) MOS PULL- UP PBn RP: READ PORT B PIN Port 8-bit bi-directional I/O ...
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Figure 27. Port D Schematic Diagram (Pins PD7 - PD0) MOS PULL- UP PDn WP: WRITE PORTD WD: WRITE DDRD RL: READ PORTD LATCH RP: READ PORTD PIN RD: READ DDRD ATtiny28L/V RD RESET ...
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Register Description Port A Data Register – PORTA Port A Control Register – PACR Port A Input Pins Address – PINA Port B Input Pins Address – PINB ATtiny28L/V 32 Bit $1B – – – Read/Write R ...
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Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND 1062F–AVR–07/06 Bit $12 PORTD7 PORTD6 PORTD5 Read/Write R/W R/W R/W Initial Value Bit 7 ...
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Timer/Counter0 Timer/Counter Prescaler ATtiny28L/V 34 The ATtiny28 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0. Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The Timer/Counter0 can either be used as a timer with an internal clock time base or as ...
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Register Description Timer/Counter0 Control Register – TCCR0 1062F–AVR–07/06 The 8-bit Timer/Counter0 can select clock source from CK, prescaled external pin. In addition, it can be stopped as described in the specification for the Timer/Counter0 Control Register (TCCR0). ...
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Timer Counter 0 – TCNT0 ATtiny28L/V 36 • Bits – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0. Table 14. Clock ...
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Watchdog Timer Register Description Watchdog Timer Control Register – WDTCR 1062F–AVR–07/06 The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in Table 15. See ...
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ATtiny28L the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must be written to WDE even though it is set to one before the disable operation starts. 2. Within the next four ...
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Hardware Modulator 1062F–AVR–07/06 ATtiny28 features a built-in hardware modulator connected to a high-current output pad, PA2. The hardware modulator generates a configurable pulse train. The on-time of a pulse can be set to a number of chip clock cycles. This ...
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ATtiny28L/V 40 Figure 31. The Hardware Modulator FROM PORTA2 WM: WRITE MODCR RM: READ MODCR Figure 32 to Figure 35 show examples on output from the Modulator. Figure 32 also ...
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Figure 34. Modulation with ONTIM = 1, MCONF = 011 CLK PA2 Note: Clock frequency: 3.64 MHz; modulation frequency: 455 kHz; duty-cycle: 25% Figure 35. Modulation with ONTIM = 3, MCONF = 001 CLK PA2 Note: Clock frequency: 3.64 ...
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ATtiny28L/V 42 Table 17. Some Common Modulator Configurations (Continued) Crystal/Resonator Carrier Frequency Frequency 2 MHz 455 kHz 2.4576 MHz 455 kHz 2.4576 MHz 455 kHz 3.2768 MHz 455 kHz 3.2768 MHz 455 kHz 3.64 MHz 455 kHz 3.64 MHz 455 ...
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Register Description Modulation Control Register – MODCR Table 18. MCONF2..0 Effect on Duty-cycle and Modulation Period MCONF2..0 On-time 000 X 001 ONTIM+1 010 ONTIM+1 011 ONTIM+1 100 2 x (ONTIM+1) 101 3 x (ONTIM+1) 110 111 X Note: In the ...
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Analog Comparator Register Description Analog Comparator Control and Status Register – ACSR ATtiny28L/V 44 The analog comparator compares the input values on the positive input PB0 (AIN0) and negative input PB1 (AIN1). When the voltage on the positive input PB0 ...
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Alternatively, ACI is cleared by writing a logical “1” to the flag. • Bit 3 – ACIE: Analog Comparator Interrupt Enable When the ACIE bit is set (one) and the I-bit in the ...
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... CKSEL3..0 to use. Default value is “0010”, internal RC oscillator with long start-up time. The status of the Fuse bits is not affected by Chip Erase. All Atmel microcontrollers have a 3-byte signature code that identifies the device. The three bytes reside in a separate address space. For the ATtiny28, they are: 1 ...
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... Parallel Programming Signal Names 1062F–AVR–07/06 Atmel’s ATtiny28 offers 2K bytes of Flash program memory. The ATtiny28 is shipped with the on-chip Flash program memory array in the erased state (i.e., contents = $FF) and ready to be programmed. This device supports a high- voltage (12V) parallel programming mode. Only minor currents (<1mA) are drawn from the +12V pin during programming ...
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Enter Programming Mode ATtiny28L/V 48 Table 22. Pin Name Mapping Signal Name in Programming Mode Pin Name RDY/BSY PD1 OE PD2 WR PD3 BS PD4 XA0 PD5 XA1 PD6 DATA PB7 - PB0 . Table 23. XA1 and XA0 Coding ...
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Chip Erase Programming the Flash 1062F–AVR–07/06 The Chip Erase command will erase the Flash memory and the Lock bits. The Lock bits are not reset until the Flash has been completely erased. The Fuse bits are not changed. Chip Erase ...
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Reading the Flash Programming the Fuse Bits Programming the Lock Bits ATtiny28L Set BS to “1”. This selects high data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait ...
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Reading the Fuse and Lock Bits Reading the Signature Bytes and Calibration Byte 1062F–AVR–07/06 The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the Flash” for details on command loading): A: Load Command “0000 ...
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ATtiny28L/V 52 Figure 39. Programming the Flash Waveforms (Continued) DATA DATA HIGH XA1 XA0 BS XTAL1 WR RDY/BSY RESET +12V OE 1062F–AVR–07/06 ...
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Parallel Programming Characteristics 1062F–AVR–07/06 Figure 40. Parallel Programming Timing t XTAL1 XHXL t DVXH Data & Contol (DATA, XA0/1, BS) WR RDY/BSY OE DATA T = 25°C ± 10 ± 10 Symbol Parameter V Programming ...
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Electrical Characteristics Absolute Maximum Ratings Operating Temperature............................. -40°C to +85/105°C Storage Temperature ..................................... -65°C to +150°C Voltage on Any Pin except RESET with Respect to Ground .............................-1. Maximum Operating Voltage ............................................ 6.0V Voltage on RESET with Respect to ...
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DC Characteristics (Continued -40°C to 85° 1.8V to 5.5V (unless otherwise noted Symbol Parameter V Analog Comparator Input ACIO Offset Voltage I Analog Comparator Input ACLK Leakage Current T Analog Comparator ACPD Propagation Delay ...
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External Clock Drive Waveforms Figure 41. External Clock VIH1 VIL1 External Clock Drive Symbol Parameter 1/t Oscillator Frequency CLCL t Clock Period CLCL t High Time CHCX t Low Time CLCX t Rise Time CLCH t Fall Time CHCL Table ...
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Typical Characteristics 1062F–AVR–07/06 The following charts show typical behavior. These figures are not tested during manu- facturing. All current consumption measurements are performed with all I/O pins configured as inputs and with internal pull-ups enabled. A sine wave generator with ...
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ATtiny28L/V 58 Figure 43. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs 1.5 2 2.5 3 Figure 44. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE ...
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Figure 45. Active Supply Current vs. V ACTIVE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32 kHz CRYSTAL 4 3.5 3 2.5 2 1.5 1 0.5 0 1.5 2 2.5 3 Figure 46. Idle Supply Current vs. Frequency IDLE ...
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ATtiny28L/V 60 Figure 47. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V 1.4 1.2 1 0.8 0.6 0.4 0.2 0 1.5 2 2.5 3 Figure 48. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED ...
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Figure 49. Idle Supply Current vs. V IDLE SUPPLY CURRENT vs. V DEVICE CLOCKED BY 32 kHz CRYSTAL 1.5 2 2.5 3 Figure 50. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT ...
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ATtiny28L/V 62 Figure 51. Power-down Supply Current vs. V POWER-DOWN SUPPLY CURRENT vs 1.5 2 2.5 3 Analog comparator offset voltage is measured as absolute offset. Figure 52. Analog Comparator Offset ...
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Figure 53. Analog Comparator Offset Voltage vs. Common Mode Voltage ( 0.5 1 Common Mode Voltage (V) Figure 54. Analog Comparator Input Leakage Current ( ...
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ATtiny28L/V 64 Figure 55. Calibrated Internal RC Oscillator Frequency vs. V CALIBRATED RC OSCILLATOR FREQUENCY vs. OPERATING VOLTAGE 1.28 1.26 1.24 1.22 1.2 1.18 1.16 1.14 1.12 1.1 2 2.5 3 Figure 56. Watchdog Oscillator Frequency vs. V 1600 1400 ...
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Sink and source capabilities of I/O ports are measured on one pin at a time. Figure 57. Pull-up Resistor Current vs. Input Voltage (V 120 T = 25˚C A 100 T = 85˚ ...
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ATtiny28L/V 66 Figure 59. I/O Pin Sink Current vs. Output Voltage. All pins except PA2 ( 0.5 1 Figure 60. I/O Pin Source Current vs. Output voltage ( ...
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Figure 61. I/O Pin Sink Current vs. Output Voltage, All Pins Except PA2 ( 0.5 Figure 62. I/O Pin Source Current vs. Output Voltage ( 25˚ ...
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ATtiny28L/V 68 Figure 63. PA2 I/O Pin Sink Current vs. Output Voltage (High Current Pin PA2; T 25° 0.5 1 1.5 Figure 64. I/O Pin Input Threshold Voltage vs. ...
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Figure 65. I/O Pin Input Hysteresis vs. V 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 ATtiny28L 25° 4.0 5 ...
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Register Summary Address Name Bit 7 $3F SREG $3E Reserved ... Reserved $20 Reserved $1F Reserved $1E Reserved $1D Reserved $1C Reserved $1B PORTA $1A PACR $19 PINA $18 Reserved $17 Reserved $16 PINB PINB7 $15 Reserved $14 Reserved $13 ...
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Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers SUB Rd, Rr Subtract Two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr ...
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Instruction Set Summary (Continued) Mnemonic Operands Description DATA TRANSFER INSTRUCTIONS LD Rd, Z Load Register Indirect Store Register Indirect MOV Rd, Rr Move between Registers LDI Rd, K Load Immediate IN Rd Port OUT P, ...
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... Ordering Code Package ATtiny28L-4AC 32A ATtiny28L-4PC 28P3 ATtiny28L-4MC 32M1-A ATtiny28L-4AI 32A (2) ATtiny28L-4AU 32A ATtiny28L-4PI 28P3 (2) ATtiny28L-4PU 28P3 ATtiny28L-4MI 32M1-A (2) ATtiny28L-4MU 32M1-A ATtiny28V-1AC 32A ATtiny28V-1PC 28P3 ATtiny28V-1MC 32M1-A ATtiny28V-1AI 32A (2) 32A ATtiny28V-1AU 28P3 ATtiny28V-1PI (2) 28P3 ATtiny28V-1PU 32M1-A ATtiny28V-1MI 32M1-A (2) ATtiny28V-1MU Package Type ATtiny28L/V ...
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Packaging Information 32A PIN 0˚~7˚ L Notes: 1. This package conforms to JEDEC reference MS-026, Variation ABA. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and ...
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A SEATING PLANE Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010"). 2325 Orchard Parkway San Jose, CA 95131 R 1062F–AVR–07/06 D ...
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Pin TOP VIEW Pin #1 Notch (0. BOTTOM VIEW Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2. 2325 Orchard Parkway San Jose, CA 95131 R ...
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Errata All revisions 1062F–AVR–07/06 No known errata. ATtiny28L/V 77 ...
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Datasheet Revision History Rev – 01/06G Rev – 01/06G Rev – 03/05F ATtiny28L/V 78 Please note that the referring page numbers in this section are referred to this docu- ment. The referring revision in this section are referring to the ...
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Table of Contents 1062F–AVR–07/06 Features................................................................................................. 1 Pin Configurations................................................................................ 1 Description ............................................................................................ 2 Block Diagram ...................................................................................................... 2 Pin Descriptions.................................................................................................... 3 Clock Options ....................................................................................................... 4 Architectural Overview......................................................................... 6 General-purpose Register File.............................................................................. 7 ALU – Arithmetic Logic Unit.................................................................................. 7 Downloadable Flash Program Memory ...
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ATtiny28L/V ii Electrical Characteristics................................................................... 53 Absolute Maximum Ratings ................................................................................ 53 DC Characteristics.............................................................................................. 53 External Clock Drive Waveforms ........................................................................ 55 External Clock Drive ........................................................................................... 55 Typical Characteristics ...................................................................... 56 Register Summary .............................................................................. 69 Instruction Set Summary ................................................................... 70 Ordering Information.......................................................................... 72 ...
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