ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 126

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

Serial Programming
Algorithm
Data Polling Flash
126
ATmega161(L)
When writing serial data to the ATmega161, data is clocked on the rising edge of SCK.
When reading data from the ATmega161, data is clocked on the falling edge of SCK.
See Figure 80, Figure 81 and Table 49 for timing details.
To program and verify the ATmega161 in the Serial Programming mode, the following
sequence is recommended (see 4-byte instruction formats in Table 48):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Program-
3. The serial programming instructions will not work if the communication is out of
4. If a chip erase is performed (must be done to erase the Flash), give RESET a
5. The Flash is programmed one page at a time. The memory page is loaded one
6. The EEPROM array is programmed one byte at a time by supplying the address
7. Any memory location can be verified by using the Read instruction, which
8. At the end of the programming session, RESET can be set high to commence
9. Power-off sequence (if needed):
When a page is being programmed into the Flash, reading an address location within
the page being programmed will give the value $FF. At the time the device is ready for a
new page, the programmed value will read correctly. This is used to determine when the
next page can be written. Note that the entire page is written simultaneously and any
address within the page can be used for polling. Data polling of the FLASH will not work
for the value $FF, so when programming this value, the user will have to wait for at least
Apply power between V
tal is not connected across pins XTAL1 and XTAL2, apply a clock signal to the
XTAL1 pin. In some systems, the programmer cannot guarantee that SCK is held
low during power-up. In this case, RESET must be given a positive pulse of at least
two XTAL1 cycles’ duration after SCK has been set to “0”.
ming Enable serial instruction to pin MOSI/PB5.
synchronization. When in sync, the second byte ($53) will echo back when issu-
ing the third byte of the Programming Enable instruction. Whether or not the
echo is correct, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give RESET a positive pulse and issue a new Programming
Enable command.
positive pulse and start over from step 2.
byte at a time by supplying the 6 LSB of the address and data together with the
Load Program Memory Page instruction. The Program Memory Page is stored
by loading the Write Program Memory Page instruction with the 7 MSB of the
address. If polling is not used, the user must wait at least t
ing the next page (please refer to Table 46). Accessing the serial programming
interface before the Flash write operation completes can result in incorrect
programming.
and data together with the appropriate Write instruction. An EEPROM memory
location is first automatically erased before new data is written. If polling is not
used, the user must wait at least t
refer to Table 46). In a chip-erased device, no $FFs in the data file(s) need to be
programmed.
returns the content at the selected address at serial output MISO/PB6.
normal operation.
Set XTAL1 to “0” (if a crystal is not used).
Set RESET to “1”.
Turn V
CC
power off.
CC
and GND while RESET and SCK are set to “0”. If a crys-
WD_EEPROM
before issuing the next byte (please
WD_FLASH
before issu-
1228D–AVR–02/07