ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 64

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

64
ATmega161(L)
The interconnection between Master and Slave CPUs with SPI is shown in Figure 41.
The PB7(SCK) pin is the Clock Output in the Master mode and is the clock input in the
Slave mode. Writing to the SPI Data Register of the Master CPU starts the SPI clock
generator, and the data written shifts out of the PB5(MOSI) pin and into the PB5(MOSI)
pin of the Slave CPU. After shifting one byte, the SPI clock generator stops, setting the
End-of-Transmission Flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR
Register is set, an interrupt is requested. The Slave Select input, PB4(SS), is set low to
select an individual Slave SPI device. The two Shift Registers in the Master and the
Slave can be considered as one distributed 16-bit circular Shift Register. This is shown
in Figure 41. When data is shifted from the Master to the Slave, data is also shifted in
the opposite direction, simultaneously. This means that during one shift cycle, data in
the Master and the Slave are interchanged.
Figure 41. SPI Master-Slave Interconnection
The system is single-buffered in the transmit direction and double-buffered in the
receive direction. This means that bytes to be transmitted cannot be written to the SPI
Data Register before the entire shift cycle is completed. When receiving data, however,
a received byte must be read from the SPI Data Register before the next byte has been
completely shifted in. Otherwise, the first byte is lost.
When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins is
overridden according to Table 22.
Table 22. SPI Pin Overrides
Note:
Pin
MOSI
MISO
SCK
SS
1. See “Alternate Functions of Port B” on page 92 for a detailed description of how to
define the direction of the user defined SPI pins.
Direction, Master SPI
User Defined
Input
User Defined
User Defined
(1)
Direction, Slave SPI
Input
User Defined
Input
Input
1228D–AVR–02/07