ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 49

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

Timer/Counter1
1228D–AVR–02/07
•
•
Figure 35 shows the block diagram for Timer/Counter1.
Figure 35. Timer/Counter1 Block Diagram
The 16-bit Timer/Counter1 can select clock source from CK, prescaled CK or an exter-
nal pin. In addition, it can be stopped as described in “Timer/Counter1 Control Register
B
Event) are found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals
are found in the Timer/Counter1 Control Registers (TCCR1A and TCCR1B). The inter-
rupt enable/disable settings for Timer/Counter1 are found in the Timer/Counter Interrupt
Mask Register (TIMSK).
When Timer/Counter1 is externally clocked, the external signal is synchronized with the
Oscillator frequency of the CPU. To assure proper sampling of the external clock, the
minimum time between two external clock transitions must be at least one internal CPU
–
TCCR1B”. The different Status Flags (Overflow, Compare Match, and Capture
Description of wake-up from Power-save mode when the timer is clocked
asynchronously: When the interrupt condition is met, the wake-up process is started
on the following cycle of the timer clock, that is, the timer is always advanced by at
least 1 before the processor can read the counter value. The Interrupt Flags are
updated three processor cycles after the processor clock has started. During these
cycles, the processor executes instructions, but the interrupt condition is not
readable and the interrupt routine has not started yet.
During asynchronous operation, the synchronization of the Interrupt Flags for the
asynchronous timer takes three processor cycles plus one timer cycle. The timer is
therefore advanced by at least 1 before the processor can read the timer value,
causing the setting of the Interrupt Flag. The output compare pin is changed on the
timer clock and is not synchronized to the processor clock.
REGISTER (TIMSK)
TIMER INT. MASK
15
15
15
15
TIMER/COUNTER1 OUTPUT COMPARE REGISTER A
T/C1 INPUT CAPTURE REGISTER (ICR1)
T/C1 OVER-
FLOW IRQ
TIMER/COUNTER1 (TCNT1)
16 BIT COMPARATOR
T/C1 COMPARE
MATCHA IRQ
8
8
8
8
7
7
7
7
TIMER INT. FLAG
REGISTER (TIFR)
T/C1 COMPARE
MATCHB IRQ
CAPTURE
TRIGGER
0
0
0
0
REGISTER A (TCCR1A)
15
15
TIMER/COUNTER1 OUTPUT COMPARE REGISTER B
T/C1 CONTROL
T/C CLEAR
T/C CLOCK SOURCE
UP/DOWN
CAPTURE IRQ
T/C1 INPUT
16 BIT COMPARATOR
CONTROL
LOGIC
8
8
REGISTER B (TCCR1B)
7
7
T/C1 CONTROL
ATmega161(L)
0
0
SPECIAL FUNCTIONS
IO REGISTER (SFIOR)
CK
T1
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