ATMEGA161-8PI Atmel, ATMEGA161-8PI Datasheet - Page 70

• Manufacturer Part Number: ATMEGA161-8PI
• Description: IC AVR MCU 16K 8MHZ IND 40-DIP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA161-8PI

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 35
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Data Converters: -
• Other names: ATMEGA1618PI

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ATmega161(L)
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If the 10(11)-bit Transmit Shift Register is empty, data is transferred from UDRn to the
Shift Register. At this time the UDREn (UART Data Register Empty) bit in the UART
Control and Status Register, UCSRnA, is set. When this bit is set (one), the UART is
ready to receive the next character. At the same time as the data is transferred from
UDRn to the 10(11)-bit Shift Register, bit 0 of the Shift Register is cleared (start bit) and
bit 9 or 10 is set (stop bit). If 9-bit data word is selected (the CHR9n bit in the UART
Control and Status Register, UCSRnB, is set), the TXB8 bit in UCSRnB is transferred to
bit 9 in the Transmit Shift Register.
On the baud rate clock following the transfer operation to the Shift Register, the start bit
is shifted out on the TXDn pin. Then follows the data, LSB first. When the stop bit has
been shifted out, the Shift Register is loaded if any new data has been written to the
UDRn during the transmission. During loading, UDREn is set. If there is no new data in
the UDRn Register to send when the stop bit is shifted out, the UDREn Flag will remain
set until UDRn is written again. When no new data has been written and the stop bit has
been present on TXDn for one bit length, the TX Complete Flag (TXCn) in UCSRnA
is set.
The TXENn bit in UCSRnB enables the UART Transmitter when set (one). When this bit
is cleared (zero), the PD1 (UART0) or PB3 (UART1) pin can be used for general I/O.
When TXENn is set, the UART Transmitter will be connected to PD1 (UART0) or PB3
(UART1), which is forced to be an output pin regardless of the setting of the DDD1 bit in
DDRD (UART0) or DDB3 in DDRB (UART1). Note that PB3 (UART1) also is used as
one of the input pins to the Analog Comparator. It is therefore not recommended to use
UART1 if the Analog Comparator is also used in the application at the same time.
A new character has been written to UDRn before the stop bit from the previous
character has been shifted out. The Shift Register is loaded when the stop bit of the
character currently being transmitted has been shifted out.
1228D–AVR–02/07