T89C51CC01UA-RLTIM Atmel, T89C51CC01UA-RLTIM Datasheet - Page 134
![IC 8051 MCU FLASH 32K 44VQFP](/photos/6/92/69202/313-44-vqfp_sml.jpg)
T89C51CC01UA-RLTIM
Manufacturer Part Number
T89C51CC01UA-RLTIM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC01CA-7CTIM.pdf
(167 pages)
2.T89C51CC01CA-7CTIM.pdf
(12 pages)
3.T89C51CC01CA-7CTIM.pdf
(32 pages)
4.T89C51CC01CA-7CTIM.pdf
(29 pages)
Specifications of T89C51CC01UA-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC01UARLTIM
Available stocks
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Part Number
Manufacturer
Quantity
Price
- T89C51CC01CA-7CTIM PDF datasheet
- T89C51CC01CA-7CTIM PDF datasheet #2
- T89C51CC01CA-7CTIM PDF datasheet #3
- T89C51CC01CA-7CTIM PDF datasheet #4
- Current page: 134 of 167
- Download datasheet (2Mb)
Registers
134
A/T89C51CC01
Table 108. ADCF Register
ADCF (S:F6h)
ADC Configuration
Reset Value = 0000 0000b
Table 109. ADCON Register
ADCON (S:F3h)
ADC Control Register
Reset Value = X000 0000b
Number
Number
CH 7
Bit
Bit
7-0
2-0
7
7
-
7
6
5
4
3
Mnemonic Description
Mnemonic Description
PSIDLE
PSIDLE
ADEOC
SCH2:0
ADSST
CH 0:7
CH 6
ADEN
Bit
Bit
6
6
-
Channel Configuration
Set to use P1.x as ADC input.
Clear to use P1.x as standart I/O port.
Pseudo Idle Mode (Best Precision)
Set to put in idle mode during conversion
Clear to convert without idle mode.
Enable/Standby Mode
Set to enable ADC
Clear for Standby mode (power dissipation 1 uW).
End Of Conversion
Set by hardware when ADC result is ready to be read. This flag can generate an
interrupt.
Must be cleared by software.
Start and Status
Set to start an A/D conversion.
Cleared by hardware after completion of the conversion
Selection of Channel to Convert
see Table 107
ADEN
CH 5
5
5
ADEOC
CH 4
4
4
ADSST
CH 3
3
3
SCH2
CH 2
2
2
SCH1
CH 1
1
1
4129N–CAN–03/08
SCH0
CH 0
0
0
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