T89C51CC01UA-RLTIM Atmel, T89C51CC01UA-RLTIM Datasheet - Page 36
![IC 8051 MCU FLASH 32K 44VQFP](/photos/6/92/69202/313-44-vqfp_sml.jpg)
T89C51CC01UA-RLTIM
Manufacturer Part Number
T89C51CC01UA-RLTIM
Description
IC 8051 MCU FLASH 32K 44VQFP
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC01CA-7CTIM.pdf
(167 pages)
2.T89C51CC01CA-7CTIM.pdf
(12 pages)
3.T89C51CC01CA-7CTIM.pdf
(32 pages)
4.T89C51CC01CA-7CTIM.pdf
(29 pages)
Specifications of T89C51CC01UA-RLTIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC01UARLTIM
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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FM0 Memory Architecture
User Space
Extra Row (XRow)
Hardware Security Byte
Column Latches
Cross Flash Memory Access
Description
36
A/T89C51CC01
The Flash memory is made up of 4 blocks (see Figure 20):
•
•
•
•
This space is composed of a 32K Bytes Flash memory organized in 256 pages of 128
Bytes. It contains the user’s application code.
This row is a part of FM0 and has a size of 128 Bytes. The extra row may contain infor-
mation for boot loader usage.
The Hardware security Byte space is a part of FM0 and has a size of 1 byte.
The 4 MSB can be read/written by software, the 4 LSB can only be read by software and
written by hardware in parallel mode.
The column latches, also part of FM0, have a size of full page (128 Bytes).
The column latches are the entrance buffers of the three previous memory locations
(user array, XROW and Hardware security byte).
The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from
external memory is impossible.
The FM1 memory can be program only by parallel programming.
The Table 24 show all software Flash access allowed.
Table 24. Cross Flash Memory Access
The memory array (user space) 32K Bytes
The Extra Row
The Hardware security bits
The column latch registers
(boot Flash)
(user Flash)
External
memory
EA = 0
FM0
FM1
Load column latch
Load column latch
Load column latch
Action
Read
Write
Read
Write
Read
Write
(user Flash)
FM0
ok
ok
ok
ok
ok
-
-
-
-
(boot Flash)
4129N–CAN–03/08
FM1
ok
-
-
-
-
-
-
-
-
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