ATMEGA32L-8MI Atmel, ATMEGA32L-8MI Datasheet - Page 67
![IC AVR MCU 32K LV 8MHZ IND 44QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA32L-8MI
Manufacturer Part Number
ATMEGA32L-8MI
Description
IC AVR MCU 32K LV 8MHZ IND 44QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA32L-8MI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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MCU Control and
Status Register –
MCUCSR
General Interrupt
Control Register –
GICR
2503Q–AVR–02/11
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in
If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate
an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is
selected, the low level must be held until the completion of the currently executing instruction to
generate an interrupt.
Table 35. Interrupt 0 Sense Control
• Bit 6 – ISC2: Interrupt Sense Control 2
The Asynchronous External Interrupt 2 is activated by the external pin INT2 if the SREG I-bit and
the corresponding interrupt mask in GICR are set. If ISC2 is written to zero, a falling edge on
INT2 activates the interrupt. If ISC2 is written to one, a rising edge on INT2 activates the inter-
rupt. Edges on INT2 are registered asynchronously. Pulses on INT2 wider than the minimum
pulse width given in
generate an interrupt. When changing the ISC2 bit, an interrupt can occur. Therefore, it is rec-
ommended to first disable INT2 by clearing its Interrupt Enable bit in the GICR Register. Then,
the ISC2 bit can be changed. Finally, the INT2 Interrupt Flag should be cleared by writing a logi-
cal one to its Interrupt Flag bit (INTF2) in the GIFR Register before the interrupt is re-enabled.
Table 36. Asynchronous External Interrupt Characteristics
• Bit 7 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-
nal pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in the MCU
General Control Register (MCUCR) define whether the External Interrupt is activated on rising
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Symbol
ISC01
t
INT
0
0
1
1
Parameter
Minimum pulse width for
asynchronous external interrupt
ISC00
0
1
0
1
INT1
R/W
JTD
R/W
7
0
7
0
Table 36
Description
The low level of INT0 generates an interrupt request.
Any logical change on INT0 generates an interrupt request.
The falling edge of INT0 generates an interrupt request.
The rising edge of INT0 generates an interrupt request.
INT0
ISC2
R/W
Table
R/W
6
0
6
0
35. The value on the INT0 pin is sampled before detecting edges.
will generate an interrupt. Shorter pulses are not guaranteed to
INT2
R/W
5
0
R
5
–
0
JTRF
R/W
R
4
–
0
4
WDRF
Condition
R/W
R
3
–
0
3
See Bit Description
BORF
R/W
R
2
–
0
2
Min
IVSEL
EXTRF
R/W
R/W
1
0
1
Typ
50
ATmega32(L)
IVCE
PORF
R/W
R/W
0
0
Max
0
MCUCSR
Units
GICR
ns
67
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