AT91FR40162-CI Atmel, AT91FR40162-CI Datasheet - Page 15

• Manufacturer Part Number: AT91FR40162-CI
• Description: IC ARM7 MCU 2M FLASH 121 PBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162-CI

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

7.8.2
7.8.3
7.9
7.9.1
7.9.2
2632D–ATARM–15-Sep-05
System Peripherals
Peripheral Interrupt Control
Peripheral Data Controller
PS: Power-saving
AIC: Advanced Interrupt Controller
Unused bits in the peripheral registers must be written at 0 for upward compatibility. These bits
read 0.
The Interrupt Control of each peripheral is controlled from the status register using the inter-
rupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and
the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt
Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt
Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask)
makes it possible to enable or disable peripheral interrupt sources with a non-interruptible sin-
gle instruction. This eliminates the need for interrupt masking at the AIC or Core level in real-
time and multi-tasking systems.
The AT91FR40162 has a 4-channel PDC dedicated to the two on-chip USARTs. One PDC
channel is dedicated to the receiver and one to the transmitter of each USART.
The user interface of a PDC channel is integrated in the memory space of each USART. It
contains a 32-bit Address Pointer Register (RPR or TPR) and a 16-bit Transfer Counter Reg-
ister (RCR or TCR). When the programmed number of transfers are performed, a status bit
indicating the end of transfer is set in the USART Status Register and an interrupt can be
generated.
The power-saving feature optimizes power consumption, enabling the software to stop the
ARM7TDMI clock (idle mode), restarting it when the module receives an interrupt (or reset). It
also enables on-chip peripheral clocks to be enabled and disabled individually, matching
power consumption and application needs.
The Advanced Interrupt Controller has an 8-level priority, individually maskable, vectored
interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from:
The AIC is extensively programmable offering maximum flexibility, and its vectoring features
reduce the real-time overhead in handling interrupts.
The AIC also features a spurious vector detection feature, which reduces spurious interrupt
handling to a minimum, and a protect mode that facilitates the debug capabilities.
• Enable/Disable/Status Registers are shadow command registers. Writing a one in the
• The external fast interrupt line (FIQ)
• The three external interrupt request lines (IRQ0 - IRQ2)
• The interrupt signals from the on-chip peripherals
Enable Register sets the corresponding bit in the Status Register. Writing a one in the
Disable Register resets the corresponding bit and the result can be read in the Status
Register. Writing a bit to zero has no effect. This register access method maximizes the
efficiency of bit manipulation, and enables modification of a register with a single non-
interruptible instruction, replacing the costly read-modify-write operation.
AT91FR40162
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