T89C51CC02CA-TISIM Atmel, T89C51CC02CA-TISIM Datasheet - Page 91
![IC 8051 MCU FLASH 16K 28SOIC](/photos/6/82/68295/453-28-soic_sml.jpg)
T89C51CC02CA-TISIM
Manufacturer Part Number
T89C51CC02CA-TISIM
Description
IC 8051 MCU FLASH 16K 28SOIC
Manufacturer
Atmel
Series
AT89C CANr
Datasheets
1.T89C51CC02CA-TDSIM.pdf
(159 pages)
2.T89C51CC02CA-TDSIM.pdf
(33 pages)
3.T89C51CC02CA-TDSIM.pdf
(29 pages)
4.T89C51CC02CA-TDSIM.pdf
(148 pages)
Specifications of T89C51CC02CA-TISIM
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC02CATISIM
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4126F–CAN–12/03
Table 61. CANEN Register
CANEN (S:CFh Read Only)
CAN Enable Message Object Registers 2
Reset Value = xxxx 0000b
Table 62. CANSIT Register
CANSIT (S:BBh Read Only) – CAN Status Interrupt Message Object Registers 2
Reset Value = xxxx0000b
Bit Number
Bit Number
7
7
-
-
7 - 4
3 - 0
7 - 4
3 - 0
6
6
-
-
Bit Mnemonic
Bit Mnemonic
ENCH3:0
SIT3:0
-
-
5
5
-
-
Description
Reserved
The values read from these bits are indeterminate. Do not set these
bits.
Enable Message Object
0 - message object is disabled => the message object is free for a
new emission or reception.
1 - message object is enabled.
This bit is resetable by re-writing the CANCONCH of the
corresponding message object.
Description
Reserved
The values read from these bits are indeterminate. Do not set these
bits.
Status of Interrupt by Message Object
0 - no interrupt.
1 - IT turned on. Reset when interrupt condition is cleared by user.
SIT3:0 = 0b 0000 1001 -> IT’s on message objects 3 & 0.
See Figure 35.
4
4
-
-
ENCH3
SIT3
3
3
ENCH2
SIT2
2
2
T89C51CC02
ENCH1
SIT1
1
1
ENCH0
SIT0
0
0
91
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