TS87C51RB2-LIA Atmel, TS87C51RB2-LIA Datasheet - Page 38

• Manufacturer Part Number: TS87C51RB2-LIA
• Description: IC MCU 8BIT 16K OTP 30MHZ 40-DIP
• Manufacturer: Atmel
• Series: 87Cr

Specifications of TS87C51RB2-LIA

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 30/20MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
SCON - Serial Control Register (98h)
Reset Value = 0000 0000b
Bit addressable
38
Bit Number
FE/SM0
7
6
5
4
3
2
1
0
7
Mnemonic
SM0
SM1
SM2
REN
RB8
TB8
Bit
FE
TI
RI
SM1
6
Framing Error bit (SMOD0=1)
Serial port Mode bit 0
Serial port Mode bit 1
Reception Enable bit
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.
Receiver Bit 8 / Ninth bit received in modes 2 and 3
Transmit Interrupt flag
modes.
Receive Interrupt flag
Serial port Mode 2 bit / Multiprocessor Communication Enable bit
SMOD0 must be set to enable access to the FE bit
SMOD0 must be cleared to enable access to the SM0 bit
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
Refer to SM1 for serial port mode selection.
SM0
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Clear to disable serial reception.
Set to enable serial reception.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and Figure 15. in the other modes.
0
0
1
1
SM2
5
SM1
0
1
0
1
Table 16. SCON Register
REN
4
Mode
0
1
2
3
TB8
3
Description
Shift Register
8-bit UART
9-bit UART
9-bit UART
Description
RB8
Baud Rate
2
F
Variable
F
Variable
XTAL
XTAL
/12 (/6 in X2 mode)
/64 or F
XTAL
Rev. C - 06 March, 2001
TI
1
/32 (/32, /16 in X2 mode)
RI
0