TS87C51RB2-LIA Atmel, TS87C51RB2-LIA Datasheet - Page 50

IC MCU 8BIT 16K OTP 30MHZ 40-DIP

TS87C51RB2-LIA

Manufacturer Part Number
TS87C51RB2-LIA
Description
IC MCU 8BIT 16K OTP 30MHZ 40-DIP
Manufacturer
Atmel
Series
87Cr

Specifications of TS87C51RB2-LIA

Core Processor
8051
Core Size
8-Bit
Speed
30/20MHz
Connectivity
UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
OTP
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Data Converters
-

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Manufacturer
Quantity
Price
Part Number:
TS87C51RB2-LIA
Manufacturer:
TEMIC
Quantity:
7
TS80C51RA2/RD2
TS83C51RB2/RC2/RD2
TS87C51RB2/RC2/RD2
6.13. Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is
weakly pulled high.
AUXR - Auxiliary Register (8Eh)
Reset Value = XXXX XX00b
Not bit addressable
50
Bit Number
7
6
5
4
3
2
1
0
7
-
Mnemonic
EXTRAM
Bit
AO
-
-
-
-
-
-
6
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
EXTRAM bit
ALE Output bit
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
See Table 5.
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
5
-
Table 27. AUXR Register
4
-
3
-
Description
2
-
EXTRAM
Rev. C - 06 March, 2001
1
AO
0

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