ATMEGA169V-8MU Atmel, ATMEGA169V-8MU Datasheet
ATMEGA169V-8MU
Specifications of ATMEGA169V-8MU
Related parts for ATMEGA169V-8MU
ATMEGA169V-8MU Summary of contents
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... I/O and Packages – 53 Programmable I/O Lines – 64-lead TQFP and 64-pad QFN/MLF • Speed Grade: – ATmega169V MHz @ 1.8 - 5.5V MHz @ 2.7 - 5.5V – ATmega169 MHz @ 2.7 - 5.5V MHz @ 4.5 - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...
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Pin Configurations Disclaimer ATmega169/V 2 Figure 1. Pinout ATmega169 LCDCAP 1 (RXD/PCINT0) PE0 2 INDEX CORNER (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) PE7 9 (SS/PCINT8) PB0 10 ...
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Overview The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize ...
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... Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications ...
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Pin Descriptions VCC GND Port A (PA7..PA0) Port B (PB7..PB0) Port C (PC7..PC0) Port D (PD7..PD0) Port E (PE7..PE0) Port F (PF7..PF0) 2514P–AVR–07/06 Digital supply voltage. Ground. Port 8-bit bi-directional I/O port with internal pull-up resistors (selected ...
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Port G (PG4..PG0) RESET XTAL1 XTAL2 AVCC AREF LCDCAP About Code Examples ATmega169/V 6 buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if ...
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AVR CPU Core Introduction Architectural Overview 2514P–AVR–07/06 This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, ...
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ALU – Arithmetic Logic Unit ATmega169/V 8 the operation is executed, and the result is stored back in the Register File – in one clock cycle. Six of the 32 registers can be used as three 16-bit indirect address register ...
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Status Register 2514P–AVR–07/06 The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated ...
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General Purpose Register File ATmega169/V 10 • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruc- tion Set Description” for detailed information. The Register File is optimized ...
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The X-register, Y-register, and Z-register Stack Pointer 2514P–AVR–07/06 The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, ...
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Instruction Execution Timing Reset and Interrupt Handling ATmega169/V 12 This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk source for the chip. No internal clock division is used. ...
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Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 252. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are ...
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Interrupt Response Time ATmega169/V 14 When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example. Assembly Code Example sei ; set Global Interrupt Enable sleep ; ...
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AVR ATmega169 Memories In-System Reprogrammable Flash Program Memory 2514P–AVR–07/06 This section describes the different memories in the ATmega169. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega169 features an ...
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SRAM Data Memory ATmega169/V 16 Figure 9 shows how the ATmega169 SRAM Memory is organized. The ATmega169 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN ...
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Data Memory Access Times EEPROM Data Memory EEPROM Read/Write Access 2514P–AVR–07/06 This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk 10. Figure 10. On-chip Data SRAM Access ...
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The EEPROM Address Register – EEARH and EEARL The EEPROM Data Register – EEDR The EEPROM Control Register – EECR ATmega169/V 18 Bit – – – EEAR7 EEAR6 EEAR5 Read/Write R/W ...
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Bit 1 – EEWE: EEPROM Write Enable The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write ...
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ATmega169/V 20 The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling inter- rupts globally) so that no interrupts will occur during execution of ...
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EEPROM Write During Power- down Sleep Mode Preventing EEPROM Corruption 2514P–AVR–07/06 The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of ...
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I/O Memory General Purpose I/O Registers The ATmega169 contains three General Purpose I/O Registers. These registers can be General Purpose I/O Register 2 – GPIOR2 General Purpose I/O Register 1 – GPIOR1 General Purpose I/O Register 0 – GPIOR0 ATmega169/V ...
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System Clock and Clock Options Clock Systems and their Distribution CPU Clock – clk CPU I/O Clock – clk I/O Flash Clock – clk FLASH Asynchronous Timer Clock – clk ASY 2514P–AVR–07/06 Figure 11 presents the principal clock systems in ...
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ADC Clock – clk ADC Clock Sources Default Clock Source ATmega169/V 24 The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives ...
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Crystal Oscillator 2514P–AVR–07/06 XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 12. Either a quartz crystal or a ceramic resonator may be ...
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Low-frequency Crystal Oscillator ATmega169/V 26 Table 5. Start-up Times for the Crystal Oscillator Clock Selection Start-up Time from Power-down and CKSEL0 SUT1..0 Power-save 0 00 258 258 ...
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... RC Oscillator and 25°C, this calibration gives a frequency within ± 10% of the nominal frequency. Using calibration methods as described in application notes available at www.atmel.com/avr it is possible to achieve ± 2% accuracy at any given V and Temperature. When this Oscillator is used as the chip clock, the Watchdog Oscilla- tor will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section “ ...
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Oscillator Calibration Register – OSCCAL External Clock ATmega169/V 28 Bit – CAL6 CAL5 Read/Write R R/W R/W Initial Value Device Specific Calibration Value • Bits 6..0 – CAL6..0: Oscillator Calibration Value Writing the calibration byte to this ...
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Clock Output Buffer Timer/Counter Oscillator System Clock Prescaler 2514P–AVR–07/06 Table 12. Start-up Times for the External Clock Selection Start-up Time from Power- SUT1..0 down and Power-save When applying an external ...
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Clock Prescale Register – CLKPR ATmega169/V 30 time the CLKPS values are written, it takes between and T1 + 2*T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, ...
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Table 13. Clock Prescaler Select CLKPS3 CLKPS2 CLKPS1 ...
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Power Management and Sleep Modes Sleep Mode Control Register – SMCR ATmega169/V 32 Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor ...
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Idle Mode ADC Noise Reduction Mode Power-down Mode Power-save Mode 2514P–AVR–07/06 When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ...
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Standby Mode Table 15. Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains Sleep Mode clk clk clk clk CPU FLASH IO Idle X ADC Noise Reduction Power-down Power-save (1) Standby Notes: 1. Only recommended ...
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Minimizing Power Consumption Analog to Digital Converter Analog Comparator 2514P–AVR–07/06 • Bit 4 - PRLCD: Power Reduction LCD Writing logic one to this bit shuts down the LCD controller. The LCD controller must be disabled and the display discharged before ...
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Brown-out Detector Internal Voltage Reference Watchdog Timer Port Pins JTAG Interface and On-chip Debug System ATmega169 the Brown-out Detector is not needed by the application, this module should be turned off. If the Brown-out Detector is enabled by ...
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System Control and Reset Resetting the AVR Reset Sources 2514P–AVR–07/06 During reset, all I/O Registers are set to their initial values, and the program starts exe- cution from the Reset Vector. The instruction placed at the Reset Vector must be ...
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ATmega169/V 38 Figure 14. Reset Logic Power-on Reset Circuit Brown-out BODLEVEL [2..0] Reset Circuit Pull-up Resistor SPIKE FILTER JTAG Reset Register Watchdog Oscillator Generator CKSEL[3:0] SUT[1:0] Table 16. Reset Characteristics Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on ...
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Power-on Reset 2514P–AVR–07/06 A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detec- tion level is defined in Table 16. The POR is activated whenever V detection level. The POR circuit can be used to trigger ...
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... V production test. This guarantees that a Brown-Out Reset will occur before voltage where correct operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for ATmega169V. Table 18. Brown-out Characteristics Symbol ...
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Watchdog Reset MCU Status Register – MCUSR 2514P–AVR–07/06 When the BOD is enabled, and V in Figure 18), the Brown-out Reset is immediately activated. When V the trigger level (V in Figure 18), the delay counter starts the MCU after ...
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Internal Voltage Reference Voltage Reference Enable Signals and Start-up Time ATmega169/V 42 • Bit 3 – WDRF: Watchdog Reset Flag This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset writing ...
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Watchdog Timer Watchdog Timer Control Register – WDTCR 2514P–AVR–07/06 The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is the typical value other V levels. By controlling the Watchdog Timer ...
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ATmega169/V 44 • Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only ...
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Timed Sequences for Changing the Configuration of the Watchdog Timer Safety Level 1 Safety Level 2 2514P–AVR–07/06 The following code example shows one assembly and one C function for turning off the WDT. The example assumes that interrupts are controlled ...
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Interrupts Interrupt Vectors in ATmega169 ATmega169/V 46 This section describes the specifics of the interrupt handling as performed in ATmega169. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling” on page 12. Table 22. ...
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Table 23 shows reset and Interrupt Vectors placement for the various combinations of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at ...
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ATmega169/V 48 When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the ...
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Moving Interrupts Between Application and Boot Space MCU Control Register – MCUCR 2514P–AVR–07/06 When the BOOTRST Fuse is programmed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts ...
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ATmega169/V 50 • Bit 0 – IVCE: Interrupt Vector Change Enable The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when ...
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External Interrupts Pin Change Interrupt Timing 2514P–AVR–07/06 The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as ...
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External Interrupt Control Register A – EICRA ATmega169/V 52 The External Interrupt Control Register A contains control bits for interrupt sense control. Bit – – – Read/Write Initial Value • Bit ...
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External Interrupt Mask Register – EIMSK External Interrupt Flag Register – EIFR 2514P–AVR–07/06 Bit PCIE1 PCIE0 – Read/Write R/W R/W R Initial Value • Bit 7 – PCIE1: Pin Change Interrupt Enable 1 When ...
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Pin Change Mask Register 1 – PCMSK1 Pin Change Mask Register 0 – PCMSK0 ATmega169/V 54 • Bit 0 – INTF0: External Interrupt Flag 0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 ...
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I/O-Ports Introduction 2514P–AVR–07/06 All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without uninten- tionally changing the direction of any other pin with ...
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Ports as General Digital I/O Configuring the Pin ATmega169/V 56 Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O. The ports ...
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Toggling the Pin Switching Between Input and Output Reading the Pin Value 2514P–AVR–07/06 Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle ...
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ATmega169/V 58 Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region ...
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Digital Input Enable and Sleep Modes 2514P–AVR–07/06 The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from input with pull-ups assigned ...
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Unconnected Pins Alternate Port Functions ATmega169 some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described ...
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Table 26 summarizes the function of the overriding signals. The pin and port indexes from Figure 26 are not shown in the succeeding tables. The overriding signals are gen- erated internally in the modules having the alternate function. Table ...
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MCU Control Register – MCUCR Alternate Functions of Port A ATmega169/V 62 Bit JTD – – Read/Write R Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written ...
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Alternate Functions of Port B 2514P–AVR–07/06 Table 29. Overriding Signals for Alternate Functions in PA3..PA0 Signal Name PA3/COM3 PUOE LCDEN • (LCDMUX>2) PUOV 0 DDOE LCDEN • (LCDMUX>2) DDOV 0 PVOE 0 PVOV 0 PTOE – DIEOE LCDEN • (LCDMUX>2) ...
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ATmega169/V 64 • OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to ...
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SS/PCINT8 – Port B, Bit 0 SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of the setting of DDB0 Slave, the SPI is ...
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Alternate Functions of Port C ATmega169/V 66 Table 32. Overriding Signals for Alternate Functions in PB3..PB0 Signal PB3/MISO/ PB2/MOSI/ Name PCINT11 PCINT10 PUOE SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD DDOE SPE • MSTR ...
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Table 34 and Table 35 relate the alternate functions of Port C to the overriding signals shown in Figure 26 on page 60. Table 34. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PC7/SEG5 PC6/SEG6 PUOE LCDEN LCDEN ...
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Alternate Functions of Port D ATmega169/V 68 The Port D pins with alternate functions are shown in Table 36. Table 36. Port D Pins Alternate Functions Port Pin Alternate Function PD7 SEG15 (LCD front plane 15) PD6 SEG16 (LCD front ...
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Table 37 and Table 38 relates the alternate functions of Port D to the overriding signals shown in Figure 26 on page 60. Table 37. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PD7/SEG15 PD6/SEG16 PUOE LCDEN • LCDEN ...
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Alternate Functions of Port E ATmega169/V 70 The Port E pins with alternate functions are shown in Table 39. Table 39. Port E Pins Alternate Functions Port Pin Alternate Function PCINT7 (Pin Change Interrupt7) PE7 CLKO (Divided System Clock) PE6 ...
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XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART operates in ...
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Alternate Functions of Port F ATmega169/V 72 Table 41. Overriding Signals for Alternate Functions in PE3..PE0 Signal PE3/AIN1/ PE2/XCK/AIN0/ Name PCINT3 PCINT2 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 XCK OUTPUT ENABLE PVOV ...
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TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Regis- ter. When the JTAG interface is enabled, this pin can ...
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Alternate Functions of Port G ATmega169/V 74 Table 44. Overriding Signals for Alternate Functions in PF3..PF0 Signal Name PF3/ADC3 PF2/ADC2 PUOE 0 0 PUOV 0 0 DDOE 0 0 DDOV 0 0 PVOE 0 0 PVOV 0 0 PTOE – ...
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Table 45 and Table 46 relates the alternate functions of Port G to the overriding signals shown in Figure 26 on page 60. Table 46. Overriding Signals for Alternate Functions in PG4 Signal Name PUOE PUOV DDOE DDOV PVOE ...
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Register Description for I/O-Ports Port A Data Register – PORTA Port A Data Direction Register – DDRA Port A Input Pins Address – PINA Port B Data Register – PORTB Port B Data Direction Register – DDRB Port B Input ...
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Port C Input Pins Address – PINC Port D Data Register – PORTD Port D Data Direction Register – DDRD Port D Input Pins Address – PIND Port E Data Register – PORTE Port E Data Direction Register – DDRE ...
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Port F Input Pins Address – PINF Port G Data Register – PORTG Port G Data Direction Register – DDRG Port G Input Pins Address – PING ATmega169/V 78 Bit PINF7 PINF6 PINF5 Read/Write R/W R/W R/W ...
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Timer/Counter0 with PWM Overview Registers 2514P–AVR–07/06 Timer/Counter0 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse ...
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Definitions Timer/Counter Clock Sources Counter Unit ATmega169/V 80 event will also set the Compare Flag (OCF0A) which can be used to generate an Output Compare interrupt request. Many register and bit references in this section are written in general form. ...
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Output Compare Unit 2514P–AVR–07/06 Depending of the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer clock (clk T0 clock source, selected by the Clock Select bits (CS02:0). When no clock source is selected ...
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Force Output Compare Compare Match Blocking by TCNT0 Write Using the Output Compare Unit ATmega169/V 82 The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare ...
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Compare Match Output Unit Compare Output Mode and Waveform Generation 2514P–AVR–07/06 The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Gener- ator uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare match. ...
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Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode ATmega169/V 84 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM01:0) ...
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Fast PWM Mode 2514P–AVR–07/06 to OCR0A is lower than the current value of TCNT0, the counter will miss the compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before ...
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Phase Correct PWM Mode ATmega169/V 86 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM ...
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Figure 33. Phase Correct PWM Mode, Timing Diagram TCNTn OCn OCn Period 1 The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each time ...
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Timer/Counter Timing Diagrams ATmega169/V 88 • The timer starts counting from a value higher than the one in OCR0A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. ...
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Timer/Counter Register Description Timer/Counter Control Register A – TCCR0A 2514P–AVR–07/06 Figure 37 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode. Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Prescaler (f ...
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ATmega169/V 90 Table 49. Waveform Generation Mode Bit Description WGM01 WGM00 Timer/Counter Mode (CTC0) (PWM0) Mode of Operation Normal PWM, Phase Correct CTC Fast PWM Note: 1. The ...
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Timer/Counter Register – TCNT0 2514P–AVR–07/06 Table 52 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to phase correct PWM mode. Table 52. Compare Output Mode, Phase Correct PWM Mode COM0A1 COM0A0 Description 0 0 Normal port operation, ...
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Output Compare Register A – OCR0A Timer/Counter 0 Interrupt Mask Register – TIMSK0 Timer/Counter 0 Interrupt Flag Register – TIFR0 ATmega169/V 92 Bit Read/Write R/W R/W R/W Initial Value The Output Compare Register A ...
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Timer/Counter0 and Timer/Counter1 Prescalers Internal Clock Source Prescaler Reset External Clock Source 2514P–AVR–07/06 Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. The Timer/Counter ...
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General Timer/Counter Control Register – GTCCR ATmega169/V 94 the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling frequency (Nyquist sampling theorem). However, due to vari- ation of the system clock ...
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Timer/Counter1 Overview 2514P–AVR–07/06 The 16-bit Timer/Counter unit allows accurate program execution timing (event man- agement), wave generation, and signal timing measurement. The main features are: • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units ...
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Registers ATmega169/V 96 Figure 40. 16-bit Timer/Counter Block Diagram Count Clear Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Note: 1. Refer to Figure 1 on page 2, Table 29 on page 63, and Table 35 on page 67 ...
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Definitions Compatibility 2514P–AVR–07/06 also set the Compare Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge triggered) event on either the ...
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Accessing 16-bit Registers ATmega169/V 98 The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each ...
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The following code examples show how atomic read of the TCNT1 Register contents. Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle. (1) Assembly Code Example TIM16_ReadTCNT1: ; Save ...
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Reusing the Temporary High Byte Register ATmega169/V 100 The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. ...
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Timer/Counter Clock Sources Counter Unit 2514P–AVR–07/06 The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0) bits located in ...
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Input Capture Unit ATmega169/V 102 how waveforms are generated on the Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see “Modes of Opera- tion” on page 107. The Timer/Counter Overflow Flag (TOV1) is set ...
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Input Capture Trigger Source Noise Canceler Using the Input Capture Unit 2514P–AVR–07/06 The ICR1 Register can only be written when using a Waveform Generation mode that utilizes the ICR1 Register for defining the counter’s TOP value. In these cases the ...
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Output Compare Units ATmega169/V 104 The 16-bit comparator continuously compares TCNT1 with the Output Compare Regis- ter (OCR1x). If TCNT equals OCR1x the comparator signals a match. A match will set the Output Compare Flag (OCF1x) at the next timer ...
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Force Output Compare Compare Match Blocking by TCNT1 Write Using the Output Compare Unit 2514P–AVR–07/06 (Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does not update this register automatically as the TCNT1 and ICR1 Register). ...
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Compare Match Output Unit ATmega169/V 106 The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Gener- ator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control ...
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Compare Output Mode and Waveform Generation Modes of Operation Normal Mode 2514P–AVR–07/06 The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no ...
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Clear Timer on Compare Match (CTC) Mode ATmega169/V 108 In Clear Timer on Compare or CTC mode (WGM13 12), the OCR1A or ICR1 Register are used to manipulate the counter resolution. In CTC mode the counter is ...
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Fast PWM Mode 2514P–AVR–07/06 The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) pro- vides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by ...
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ATmega169/V 110 When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare ...
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Phase Correct PWM Mode 2514P–AVR–07/06 The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, ...
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ATmega169/V 112 The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOT- TOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accordingly at the same timer ...
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Phase and Frequency Correct PWM Mode 2514P–AVR–07/06 The phase and frequency correct Pulse Width Modulation, or phase and frequency cor- rect PWM mode (WGM13 provides a high resolution phase and frequency correct PWM waveform generation option. ...
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ATmega169/V 114 The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or ICR1 is used for defining the TOP value, ...
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Timer/Counter Timing Diagrams 2514P–AVR–07/06 The Timer/Counter is a synchronous design and the timer clock (clk shown as a clock enable signal in the following figures. The figures include information on when Interrupt Flags are set, and when the OCR1x Register ...
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ATmega169/V 116 Figure 51. Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn TOP - 1 (CTC and FPWM) TCNTn TOP - 1 (PC and PFC PWM) TOVn (FPWM) and ICFn (if used as TOP) OCRnx ...
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Timer/Counter Register Description Timer/Counter1 Control Register A – TCCR1A 2514P–AVR–07/06 Bit COM1A1 COM1A0 COM1B1 Read/Write R/W R/W R/W Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit ...
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ATmega169/V 118 Table 57 shows the COM1x1:0 bit functionality when the WGM13:0 bits are set to the phase correct or the phase and frequency correct, PWM mode. Table 57. Compare Output Mode, Phase Correct and Phase and Frequency Correct (1) ...
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Table 58. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...
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Timer/Counter1 Control Register C – TCCR1C ATmega169/V 120 (ICF1), and this can be used to cause an Input Capture Interrupt, if this interrupt is enabled. When the ICR1 is used as TOP value (see description of the WGM13:0 bits located ...
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Timer/Counter1 – TCNT1H and TCNT1L Output Compare Register 1 A – OCR1AH and OCR1AL Output Compare Register 1 B – OCR1BH and OCR1BL 2514P–AVR–07/06 A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear ...
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Input Capture Register 1 – ICR1H and ICR1L Timer/Counter1 Interrupt Mask Register – TIMSK1 ATmega169/V 122 Bit Read/Write R/W R/W R/W Initial Value The Input Capture is updated with the counter (TCNT1) value each ...
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Timer/Counter1 Interrupt Flag Register – TIFR1 2514P–AVR–07/06 Bit – – ICF1 Read/Write R R R/W Initial Value • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event ...
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Timer/Counter2 with PWM and Asynchronous Operation Overview Registers ATmega169/V 124 Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • ...
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Definitions Timer/Counter Clock Sources Counter Unit 2514P–AVR–07/06 ment) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk The double buffered Output Compare ...
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Output Compare Unit ATmega169/V 126 top Signalizes that TCNT2 has reached maximum value. bottom Signalizes that TCNT2 has reached minimum value (zero). Depending on the mode of operation used, the counter is cleared, incremented, or dec- remented at each timer ...
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Force Output Compare Compare Match Blocking by TCNT2 Write Using the Output Compare Unit 2514P–AVR–07/06 The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) ...
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Compare Match Output Unit Compare Output Mode and Waveform Generation ATmega169/V 128 The Compare Output mode (COM2A1:0) bits have two functions. The Waveform Gener- ator uses the COM2A1:0 bits for defining the Output Compare (OC2A) state at the next compare ...
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Modes of Operation Normal Mode Clear Timer on Compare Match (CTC) Mode 2514P–AVR–07/06 The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Generation mode (WGM21:0) and ...
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Fast PWM Mode ATmega169/V 130 compare match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur. For generating a waveform output in CTC mode, the ...
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Phase Correct PWM Mode 2514P–AVR–07/06 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches MAX. If the interrupt is enabled, the interrupt handler routine can be used for updating the com- pare value. In fast PWM mode, ...
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ATmega169/V 132 Figure 59. Phase Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period 1 The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOT- TOM. The Interrupt Flag can be used to generate an interrupt each ...
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Timer/Counter Timing Diagrams 2514P–AVR–07/06 • The timer starts counting from a value higher than the one in OCR2A, and for that reason misses the Compare Match and hence the OCn change that would have happened on the way up. The ...
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ATmega169/V 134 Figure 62. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx Figure 63 shows the setting of OCF2A and the clearing of TCNT2 in CTC ...
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Timer/Counter Register Description Timer/Counter Control Register A– TCCR2A 2514P–AVR–07/06 Bit FOC2A WGM20 COM2A1 Read/Write W R/W R/W Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only ...
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ATmega169/V 136 • Bit 5:4 – COM2A1:0: Compare Match Output Mode A These bits control the Output Compare pin (OC2A) behavior. If one or both of the COM2A1:0 bits are set, the OC2A output overrides the normal port functionality of ...
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Timer/Counter Register – TCNT2 Output Compare Register A – OCR2A 2514P–AVR–07/06 • Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see Table 65. Table 65. Clock Select ...
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Asynchronous operation of the Timer/Counter Asynchronous Status Register – ASSR ATmega169/V 138 Bit – – – Read/Write Initial Value • Bit 4 – EXCLK: Enable External Clock Input When EXCLK is ...
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Asynchronous Operation of Timer/Counter2 2514P–AVR–07/06 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be corrupted. A safe procedure for switching ...
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Timer/Counter2 Interrupt Mask Register – TIMSK2 ATmega169/V 140 • Description of wake up from Power-save or ADC Noise Reduction mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the ...
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Timer/Counter2 Interrupt Flag Register – TIFR2 2514P–AVR–07/06 Bit – – – Read/Write Initial Value • Bit 1 – OCF2A: Output Compare Flag 2 A The OCF2A bit is set (one) when ...
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Timer/Counter Prescaler General Timer/Counter Control Register – GTCCR ATmega169/V 142 Figure 64. Prescaler for Timer/Counter2 clk clk I/O T2S Clear TOSC1 AS2 PSR2 CS20 CS21 CS22 The clock source for Timer/Counter2 is named clk the main system I/O clock clk ...
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Serial Peripheral Interface – SPI 2514P–AVR–07/06 The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega169 and peripheral devices or between several AVR devices. The ATmega169 SPI includes the following features: • Full-duplex, Three-wire Synchronous Data Transfer ...
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ATmega169/V 144 each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line. When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 66. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 60. (1) Table ...
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ATmega169/V 146 SPI_MasterInit: ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0) out SPCR,r17 ret SPI_MasterTransmit: ; Start transmission of data (r16) out SPDR,r16 Wait_Transmit: ; ...
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The following code examples show how to initialize the SPI as a Slave and how to per- form a simple reception. (1) Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi r17,(1<<DD_MISO) out DDR_SPI,r17 ; Enable ...
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SS Pin Functionality Slave Mode Master Mode SPI Control Register – SPCR ATmega169/V 148 When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and ...
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Bit 4 – MSTR: Master/Slave Select This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero configured as an input and is driven low while MSTR is ...
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SPI Status Register – SPSR SPI Data Register – SPDR ATmega169/V 150 Bit SPIF WCOL – Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer ...
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Data Modes 2514P–AVR–07/06 There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 67 and Figure 68. Data ...
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USART Overview ATmega169/V 152 The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART highly flexible serial communication device. The main features are: • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation ...
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AVR USART vs. AVR UART – Compatibility Clock Generation 2514P–AVR–07/06 The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all ...
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Internal Clock Generation – The Baud Rate Generator ATmega169/V 154 Figure 70. Clock Generation Logic, Block Diagram UBRR fosc UBRR+1 Prescaling Down-Counter OSC Sync Register xcki XCK xcko Pin DDR_XCK Signal description: txclk Transmitter clock (Internal Signal). rxclk Receiver base ...
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Double Speed Operation (U2X) External Clock 2514P–AVR–07/06 Table 71. Equations for Calculating Baud Rate Register Setting Equation for Calculating Operating Mode Asynchronous Normal BAUD mode (U2X = 0) Asynchronous Double Speed mode (U2X = 1) BAUD Synchronous Master mode BAUD ...
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Synchronous Clock Operation When synchronous mode is used (UMSEL = 1), the XCK pin will be used as either clock Frame Formats ATmega169/V 156 input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or ...
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Parity Bit Calculation USART Initialization 2514P–AVR–07/06 Sp Stop bit, always high. IDLE No transfers on the communication line (RxD or TxD). An IDLE line must be high. The frame format used by the USART is set by the UCSZ2:0, UPM1:0 ...
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ATmega169/V 158 The following simple USART initialization code examples show one assembly and one C function that are equal in functionality. The examples assume asynchronous opera- tion using polling (no interrupts enabled) and a fixed frame format. The baud rate ...
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Data Transmission – The USART Transmitter Sending Frames with Data Bit 2514P–AVR–07/06 The USART Transmitter is enabled by setting the Transmit Enable (TXEN) bit in the UCSRB Register. When the Transmitter is enabled, the normal port operation ...
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Sending Frames with 9 Data Bit ATmega169/V 160 If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8 bit in UCSRB before the low byte of the character is written to UDR. The ...
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Transmitter Flags and Interrupts Parity Generator Disabling the Transmitter 2514P–AVR–07/06 The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDRE) and Transmit Complete (TXC). Both flags can be used for generating interrupts. The Data Register ...
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Data Reception – The USART Receiver Receiving Frames with Data Bits ATmega169/V 162 The USART Receiver is enabled by writing the Receive Enable (RXEN) bit in the UCSRB Register to one. When the Receiver is enabled, the ...
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Receiving Frames with 9 Data Bits 2514P–AVR–07/06 If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8 bit in UCSRB before reading the low bits from the UDR. This rule applies to the FE, DOR ...
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Receive Compete Flag and Interrupt Receiver Error Flags ATmega169/V 164 The receive function example reads all the I/O Registers into the Register File before any computation is done. This gives an optimal receive buffer utilization since the buffer location read ...
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Parity Checker Disabling the Receiver Flushing the Receive Buffer Asynchronous Data Reception 2514P–AVR–07/06 The Parity Checker is active when the high USART Parity mode (UPM1) bit is set. Type of Parity Check to be performed (odd or even) is selected ...
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Asynchronous Clock Recovery Asynchronous Data Recovery ATmega169/V 166 The clock recovery logic synchronizes internal clock to the incoming serial frames. Fig- ure 73 illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 ...
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Asynchronous Operational Range 2514P–AVR–07/06 Figure 75 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. Figure 75. Stop Bit Sampling and Next Start Bit Sampling RxD Sample (U2X = ...
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ATmega169/V 168 Table 72. Recommended Maximum Receiver Baud Rate Error for Normal Speed Mode (U2X = (Data+Parity Bit) R (%) R slow 5 93.20 106.67 6 94.12 105.79 7 94.81 105.11 8 95.36 104.58 9 95.81 104.14 ...
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Multi-processor Communication Mode Using MPCM 2514P–AVR–07/06 Setting the Multi-processor Communication mode (MPCM) bit in UCSRA enables a fil- tering function of incoming frames received by the USART Receiver. Frames that do not contain address information will be ignored and not ...
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USART Register Description USART I/O Data Register – UDR USART Control and Status Register A – UCSRA ATmega169/V 170 Bit Read/Write R/W R/W R/W Initial Value The USART Transmit Data Buffer Register and USART ...
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Bit 5 – UDRE: USART Data Register Empty The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive new data. If UDRE is one, the buffer is empty, and therefore ready to be written. The ...
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USART Control and Status Register B – UCSRB ATmega169/V 172 Bit RXCIE TXCIE UDRIE Read/Write R/W R/W R/W Initial Value • Bit 7 – RXCIE: RX Complete Interrupt Enable Writing this bit to one ...
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USART Control and Status Register C – UCSRC 2514P–AVR–07/06 Bit – UMSEL UPM1 Read/Write R R/W R/W Initial Value • Bit 6 – UMSEL: USART Mode Select This bit selects between asynchronous and synchronous ...
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USART Baud Rate Registers – UBRRL and UBRRH ATmega169/V 174 • Bit 2:1 – UCSZ1:0: Character Size The UCSZ1:0 bits combined with the UCSZ2 bit in UCSRB sets the number of data bits (Character SiZe frame the Receiver ...
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Examples of Baud Rate Setting Table 79. Examples of UBRR Settings for Commonly Used Oscillator Frequencies f = 1.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 25 0.2% 51 4800 12 0.2% 25 9600 6 ...
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Table 80. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...
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Table 81. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2X = 0 Rate (bps) UBRR Error UBRR 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% 103 14.4k 34 ...
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Table 82. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2X = 0 U2X = 1 Rate (bps) UBRR Error UBRR 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...
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USI – Universal Serial Interface Overview 2514P–AVR–07/06 The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code ...
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Functional Descriptions Three-wire Mode ATmega169/V 180 The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It can also generate wait states by holding the clock pin low after a start ...
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SPI Master Operation Example 2514P–AVR–07/06 The Three-wire mode timing is shown in Figure 78. At the top of the figure is a USCK cycle reference. One bit is shifted into the USI Shift Register (USIDR) for each of these cycles. ...
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SPI Slave Operation Example ATmega169/V 182 The following code demonstrates how to use the USI module as a SPI Master with max- imum speed (fsck = fck/4): SPITransfer_Fast: sts USIDR,r16 ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC) ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK) sts USICR,r16 ; MSB sts USICR,r17 ...
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Two-wire Mode 2514P–AVR–07/06 Note that the first two instructions is for initialization only and needs only to be executed once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop is repeated until the USI Counter Overflow Flag ...
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ATmega169/V 184 Figure 80. Two-wire Mode, Typical Timing Diagram SDA SCL ADDRESS R Referring to the timing diagram (Figure 80.), a bus transfer involves the following steps: 1. The a start ...
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Start Condition Detector Clock speed considerations. Alternative USI Usage Half-duplex Asynchronous Data Transfer 4-bit Counter 12-bit Timer/Counter Edge Triggered External Interrupt Software Interrupt USI Register Descriptions USI Data Register – USIDR 2514P–AVR–07/06 The start condition detector is shown in Figure ...
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USI Status Register – USISR ATmega169/V 186 The output pin in use SDA depending on the wire mode, is connected via the out- put latch to the most significant bit (bit 7) of the Data Register. The output ...
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USI Control Register – USICR 2514P–AVR–07/06 The 4-bit counter increments by one for each clock generated either by the external clock edge detector Timer/Counter0 Compare Match software using USI- CLK or USITC strobe bits. The clock ...
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ATmega169/V 188 Table 83. Relations between USIWM1..0 and the USI Operation USIWM1 USIWM0 Description 0 0 Outputs, clock hold, and start detector disabled. Port pins operates as normal Three-wire mode. Uses DO, DI, and USCK pins. The Data ...
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Bit 3..2 – USICS1..0: Clock Source Select These bits set the clock source for the Shift Register and counter. The data output latch ensures that the output is changed at the opposite edge of the sampling of the ...
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Analog Comparator ADC Control and Status Register B – ADCSRB Analog Comparator Control and Status Register – ACSR ATmega169/V 190 The Analog Comparator compares the input values on the positive pin AIN0 and nega- tive pin AIN1. When the voltage ...
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Active and Idle mode. When changing the ACD bit, the Analog Compar- ator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed. • Bit 6 ...
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Analog Comparator Multiplexed Input Digital Input Disable Register 1 – DIDR1 ATmega169/V 192 It is possible to select any of the ADC7..0 pins to replace the negative input to the Ana- log Comparator. The ADC multiplexer is used to select ...
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Analog to Digital Converter Features 2514P–AVR–07/06 • 10-bit Resolution • 0.5 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 13 µs - 260 µs Conversion Time (50 kHz to 1 MHz ADC clock) • kSPS ...
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Operation ATmega169/V 194 Figure 83. Analog to Digital Converter Block Schematic 8-BIT DATA BUS ADC MULTIPLEXER SELECT (ADMUX) MUX DECODER AVCC INTERNAL REFERENCE AREF GND BANDGAP REFERENCE ADC7 ADC6 POS. ADC5 INPUT MUX ADC4 ADC3 ADC2 ADC1 ADC0 NEG. INPUT ...
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Starting a Conversion 2514P–AVR–07/06 to Data Registers is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is read, neither register is updated and the result from the con- version is lost. When ADCH ...
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Prescaling and Conversion Timing ATmega169/V 196 The ADSC bit will be read as one during a conversion, independently of how the conver- sion was started. Figure 85. ADC Prescaler ADEN START CK ADPS0 ADPS1 ADPS2 By default, the successive approximation ...
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In Free Running mode, a new conversion will be started immediately after the conver- sion completes, while ADSC remains high. For a summary of conversion times, see Table 87. Figure 86. ADC Timing Diagram, First Conversion (Single Conversion Mode) ...
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ATmega169/V 198 Figure 89. ADC Timing Diagram, Free Running Conversion One Conversion 11 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete Table 87. ADC Conversion Time Condition First conversion Normal conversions, single ended Auto Triggered conversions Next Conversion ...
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Changing Channel or Reference Selection ADC Input Channels ADC Voltage Reference 2514P–AVR–07/06 The MUXn and REFS1:0 bits in the ADMUX Register are single buffered through a tem- porary register to which the CPU has random access. This ensures that the ...
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ADC Noise Canceler Analog Input Circuitry ATmega169/V 200 external voltage external voltage is applied to the AREF pin, the user may switch between AVCC and 1.1V as reference selection. The first ADC conversion result after switching reference voltage ...