ATMEGA169V-8MU Atmel, ATMEGA169V-8MU Datasheet - Page 285
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ATMEGA169V-8MU
Manufacturer Part Number
ATMEGA169V-8MU
Description
IC AVR MCU 16K 8MHZ 1.8V 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Table 130. Serial Programming Instruction Set (Continued)
Note:
SPI Serial Programming
Characteristics
Programming via the
JTAG Interface
Programming Specific JTAG
Instructions
2514P–AVR–07/06
Instruction
Read Extended Fuse Bits
Read Calibration Byte
Poll RDY/BSY
a = address high bits, b = address low bits, H = 0 - Low byte, 1 - High Byte, o = data out, i = data in, x = don’t care
0101 0000
0011 1000
1111 0000
Byte 1
For characteristics of the SPI module see “SPI Timing Characteristics” on page 301.
Programming through the JTAG interface requires control of the four JTAG specific
pins: TCK, TMS, TDI, and TDO. Control of the reset and clock pins is not required.
To be able to use the JTAG interface, the JTAGEN Fuse must be programmed. The
device is default shipped with the fuse programmed. In addition, the JTD bit in MCUCSR
must be cleared. Alternatively, if the JTD bit is set, the external reset can be forced low.
Then, the JTD bit will be cleared after two chip clocks, and the JTAG pins are available
for programming. This provides a means of using the JTAG pins as normal port pins in
Running mode while still allowing In-System Programming via the JTAG interface. Note
that this technique can not be used when using the JTAG pins for Boundary-scan or On-
chip Debug. In these cases the JTAG pins must be dedicated for this purpose.
During programming the clock frequency of the TCK Input must be less than the maxi-
mum frequency of the chip. The System Clock Prescaler can not be used to divide the
TCK Clock Input into a sufficiently low frequency.
As a definition in this datasheet, the LSB is shifted in and out first of all Shift Registers.
The Instruction Register is 4-bit wide, supporting up to 16 instructions. The JTAG
instructions useful for programming are listed below.
The OPCODE for each instruction is shown behind the instruction name in hex format.
The text describes which Data Register is selected as path between TDI and TDO for
each instruction.
The Run-Test/Idle state of the TAP controller is used to generate internal clocks. It can
also be used as an idle state between JTAG sequences. The state machine sequence
for changing the instruction word is shown in Figure 130.
0000 1000
000x xxxx
0000 0000
Byte 2
Instruction Format
xxxx xxxx
0000 0000
xxxx xxxx
Byte 3
oooo oooo
oooo oooo
xxxx xxxo
Byte4
Operation
Read Extended Fuse bits. “0” = pro-
grammed, “1” = unprogrammed. See
Table 118 on page 267 for details.
Read Calibration Byte
If o = “1”, a programming operation is
still busy. Wait until this bit returns to
“0” before applying another command.
ATmega169/V
285
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