ATMEGA169V-8MU Atmel, ATMEGA169V-8MU Datasheet - Page 236
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ATMEGA169V-8MU
Manufacturer Part Number
ATMEGA169V-8MU
Description
IC AVR MCU 16K 8MHZ 1.8V 64-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA169V-8MU
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-MLF®, 64-QFN
For Use With
ATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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MCU Status Register –
MCUSR
Boundary-scan Chain
Scanning the Digital Port Pins Figure 109 shows the Boundary-scan Cell for a bi-directional port pin with pull-up func-
236
ATmega169/V
The MCU Status Register provides information on which reset source caused an MCU
reset.
• Bit 4 – JTRF: JTAG Reset Flag
This bit is set if a reset is being caused by a logic one in the JTAG Reset Register
selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or
by writing a logic zero to the flag.
The Boundary-scan chain has the capability of driving and observing the logic levels on
the digital I/O pins, as well as the boundary between digital and analog logic for analog
circuitry having off-chip connection.
tion. The cell consists of a standard Boundary-scan cell for the Pull-up Enable – PUExn
– function, and a bi-directional pin cell that combines the three signals Output Control –
OCxn, Output Data – ODxn, and Input Data – IDxn, into only a two-stage Shift Register.
The port and pin indexes are not used in the following description
The Boundary-scan logic is not included in the figures in the datasheet. Figure 110
shows a simple digital port pin as described in the section “I/O-Ports” on page 55. The
Boundary-scan details from Figure 109 replaces the dashed box in Figure 110.
When no alternate port function is present, the Input Data – ID – corresponds to the
PINxn Register value (but ID has no synchronizer), Output Data corresponds to the
PORT Register, Output Control corresponds to the Data Direction – DD Register, and
the Pull-up Enable – PUExn – corresponds to logic expression PUD · DDxn · PORTxn.
Digital alternate port functions are connected outside the dotted box in Figure 110 to
make the scan chain read the actual pin value. For Analog function, there is a direct
connection from the external pin to the analog circuit, and a scan chain is inserted on
the interface between the digital logic and the analog circuitry.
Bit
Read/Write
Initial Value
R
7
–
0
R
6
–
0
R
5
–
0
JTRF
R/W
4
WDRF
R/W
3
See Bit Description
BORF
R/W
2
EXTRF
R/W
1
PORF
R/W
2514P–AVR–07/06
0
MCUSR
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