AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 119

• Manufacturer Part Number: AT80C51SND1C-ROTUL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

16.6.3
16.6.3.1
16.6.3.2
16.6.3.3
16.6.3.4
16.6.3.5
4109L–8051–02/08
Data Transmitter
Configuration
Data Loading
Data Transmission
End of Transmission
Busy Status
Figure 16-16. Data Controller Configuration Flows
For transmitting data to the card user must first configure the data controller in transmission
mode by setting the DATDIR bit in MMCON1 register.
Figure 16-17 summarizes the data stream transmission flows in both polling and interrupt modes
while Figure 16-18 summarizes the data block transmission flows in both polling and interrupt
modes, these flows assume that block length is greater than 16 data.
Data is loaded in the FIFO by writing to MMDAT register. Number of data loaded may vary from
1 to 16 Bytes. Then if necessary (more than 16 Bytes to send) user must wait that one FIFO
becomes empty (F1EI or F2EI set) before loading 8 new data.
Transmission is enabled by setting and clearing DATEN bit in MMCON1 register.
Data is transmitted immediately if the response has already been received, or is delayed after
the response reception if its status is correct. In both cases transmission is delayed if a card
sends a busy state on the data line until the end of this busy condition.
According to the MMC specification, the data transfer from the host to the card may not start
sooner than 2 MMC clock periods after the card response was received (formally N
ter). To address all card types, this delay can be programmed using DATD1:0 bits in MMCON2
register from 3 MMC clock periods when DATD1:0 bits are cleared to 9 MMC clock periods
when DATD1:0 bits are set, by step of 2 MMC clock periods.
The end of a data frame (block or stream) transmission is signalled to you by the EOFI flag in
MMINT register. This flag may generate an MMC interrupt request as detailed in Section "Inter-
rupt", page 123.
In data stream mode, EOFI flag is set, after reception of the End bit. This assumes user has pre-
viously sent the STOP command to the card, which is the only way to stop stream transfer.
In data block mode, EOFI flag is set, after reception of the CRC status token (see Figure 16-7).
2 other flags in MMSTA register: DATFS and CRC16S report a status on the frame sent. DATFS
indicates if the CRC status token format is correct or not, and CRC16S indicates if the card has
found the CRC16 of the block correct or not.
As shown in Figure 16-7 the card uses a busy token during a block write operation. This busy
status is reported to you by the CBUSY flag in MMSTA register and by the MCBI flag in MMINT
Configure Format
Configuration
Data Stream
DFMT = 0
Data Single Block
Configure Format
BLEN3:0 = XXXXb
Configuration
MBLOCK = 0
DFMT = 1
AT8xC51SND1C
Data Multi-Block
Configure Format
BLEN3:0 = XXXXb
Configuration
MBLOCK = 1
DFMT = 1
WR
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