AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 144

• Manufacturer Part Number: AT80C51SND1C-ROTUL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

144
AT8xC51SND1C
Reset Value = 0000 0000b
Table 127. SBUF Register
SBUF (S:99h) – Serial Buffer Register
Reset value = XXXX XXXXb
Table 128. SADDR Register
Number
Number
7 - 0
SD7
Bit
Bit
7
6
5
4
3
2
1
0
7
Mnemonic Description
Mnemonic Description
SD7:0
REN
SM0
SM1
SM2
TB8
RB8
SD6
Bit
FE
Bit
RI
TI
6
Framing Error Bit
To select this function, set SMOD0 bit in PCON register.
Set by hardware to indicate an invalid stop bit.
Must be cleared by software.
Serial Port Mode Bit 0
Refer to Table 124 for mode selection.
Serial Port Mode Bit 1
Refer to Table 124 for mode selection.
Serial Port Mode Bit 2
Set to enable the multiprocessor communication and automatic address
recognition features.
Clear to disable the multiprocessor communication and automatic address
recognition features.
Receiver Enable Bit
Set to enable reception.
Clear to disable reception.
Transmit Bit 8
Modes 0 and 1: Not used.
Modes 2 and 3: Software writes the ninth data bit to be transmitted to TB8.
Receiver Bit 8
Mode 0: Not used.
Mode 1 (SM2 cleared): Set or cleared by hardware to reflect the stop bit
received.
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth bit
received.
Transmit Interrupt Flag
Set by the transmitter after the last data bit is transmitted.
Must be cleared by software.
Receive Interrupt Flag
Set by the receiver after the stop bit of a frame has been received.
Must be cleared by software.
Serial Data Byte
Read the last data received by the serial I/O Port.
Write the data to be transmitted by the serial I/O Port.
SD5
5
SD4
4
SD3
3
SD2
2
SD1
1
4109L–8051–02/08
SD0
0