AT91SAM7S512-MU-999 Atmel, AT91SAM7S512-MU-999 Datasheet - Page 306
AT91SAM7S512-MU-999
Manufacturer Part Number
AT91SAM7S512-MU-999
Description
IC MCU ARM7 512KB FLASH 64-VQFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S512-MU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 306 of 779
- Download datasheet (11Mb)
29.7.1
Register Name:
Access Type:
• START: Send a START Condition
0 = No effect.
1 = A frame beginning with a START bit is transmitted according to the features defined in the mode register.
This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a
write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR).
• STOP: Send a STOP Condition
0 = No effect.
1 = STOP Condition is sent just after completing the current byte transmission in master read mode.
• MSEN: TWI Master Transfer Enabled
0 = No effect.
1 = If MSDIS = 0, the master data transfer is enabled.
• MSDIS: TWI Master Transfer Disabled
0 = No effect.
1 = The master data transfer is disabled, all pending data is transmitted. The shifter and holding characters (if they contain
data) are transmitted in case of write operation. In read operation, the character being transferred must be completely
received before disabling.
• SWRST: Software Reset
0 = No effect.
1 = Equivalent to a system reset.
306
SWRST
– In single data byte master read, the START and STOP must both be set.
– In multiple data bytes master read, the STOP must be set after the last data received but one.
– In master read mode, if a NACK bit is received, the STOP is automatically performed.
– In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically
31
23
15
–
–
–
7
sent.
AT91SAM7S Series Preliminary
TWI Control Register
30
22
14
TWI_CR
Write-only
–
–
–
6
–
29
21
13
–
–
–
5
–
28
20
12
–
–
–
4
–
MSDIS
27
19
11
–
–
–
3
MSEN
26
18
10
–
–
–
2
STOP
25
17
–
–
9
–
1
6175K–ATARM–30-Aug-10
START
24
16
–
–
8
–
0
Related parts for AT91SAM7S512-MU-999
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
DEV KIT FOR AVR/AVR32
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet: