AT91SAM7S512-MU-999 Atmel, AT91SAM7S512-MU-999 Datasheet - Page 495
AT91SAM7S512-MU-999
Manufacturer Part Number
AT91SAM7S512-MU-999
Description
IC MCU ARM7 512KB FLASH 64-VQFN
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM7S512-MU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
For Use With
AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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34.6.11
Register Name:
Access Type:
Only the first 16 bits (internal channel counter size) are significant.
• CPRD: Channel Period
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
6175K–ATARM–30-Aug-10
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being 1, 2, 4, 8, 16, 32, 64, 128,
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula becomes, respectively:
31
23
15
7
256, 512, or 1024). The resulting period formula will be:
(
--------------------------------- -
(
-------------------------------------------- -
256, 512, or 1024). The resulting period formula will be:
(
--------------------------------------------
(
-------------------------------------------------------
X
CRPD
2
2
×
×
×
PWM Channel Period Register
MCK
X
CPRD
CPRD
MCK
MCK
×
MCK
×
CPRD
DIVA
)
×
DIVA
30
22
14
)
PWM_CPRD[0..X-1]
6
)
Read/Write
or
)
(
------------------------------------------------ -
CRPD
or
(
-------------------------------------------------------
2
MCK
×
×
CPRD
DIVAB
29
21
13
MCK
5
×
)
DIVB
)
28
20
12
4
CPRD
CPRD
CPRD
CPRD
AT91SAM7S Series Preliminary
27
19
11
3
26
18
10
2
25
17
9
1
24
16
8
0
495
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