SX18AC/SO Parallax Inc, SX18AC/SO Datasheet - Page 26

• Manufacturer Part Number: SX18AC/SO
• Description: IC MCU 2K FLASH 50MHZ SO-18
• Manufacturer: Parallax Inc
• Series: SXr

Specifications of SX18AC/SO

• Core Processor: RISC
• Core Size: 8-Bit
• Speed: 50MHz
• Number Of I /o: 12
• Program Memory Size: 3KB (2K x 12)
• Program Memory Type: FLASH
• Ram Size: 137 x 8
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-SOIC
• Voltage - Supply (vcc/vdd): -
• Eeprom Size: -
• Data Converters: -
• Peripherals: -
• Connectivity: -

SX18AC / SX20AC / SX28AC
14.0 REGISTER STATES UPON RESET
The effect of a reset operation on a register depends on
the register and the type of reset operation. Some regis-
ters are initialized to specific values, some are left
unchanged (for wakeup and brown-out resets), and some
are initialized to an unknown value. A register that starts
© 1998 Scenix Semiconductor, Inc. All rights reserved.
W
OPTION
MODE
RTCC (01h)
PC (02h)
STATUS (03h)
FSR (04h)
RA/RB/RC
Direction
RA/RB/RC Data
Other File Registers -
SRAM
CMP_B
WKPND_B
WKED_B
WKEN_B
ST_B/ST_C
LVL_A/LVL_B/LVL_C
PLP_A/PLP_B/PLP_C
Watchdog Counter
NOTE:
NOTE:
Register
1. Watchdog reset during SLEEP mode: 00
2. External reset during SLEEP mode: 10
Watchdog reset during Active mode: 01
External reset during Active mode: Unchanged
Undefined
FFh
0Fh
Undefined
0Fh
Bits 0-2: Unde-
fined
Bits 3-4: 1
Bits 5-7: 0
Undefined
FFh
Undefined
Undefined
Bits 0, 6-7: 1
Bits 1-5: Unde-
fined
FFh
FFh
FFh
FFh
FFh
FFh
Undefined
Power-On
Table 14-1. Register States Upon Reset
Unchanged
FFh
0Fh
Unchanged
0Fh
Bits 0-2: Unde-
fined
Bits 3-4: Unch.
Bits 5-7: 0
Bits 0-6: Unde-
fined
Bit 7: 1
FFh
Unchanged
Unchanged
Bits 0, 6-7: 1
Bits 1-5: Unde-
fined
Unchanged
FFh
FFh
FFh
FFh
FFh
Unchanged
Wakeup
- 26 -
with an unknown value should be initialized by the soft-
ware to a known value; you cannot simply test the initial
state and rely on it starting in that state consistently.
Table 14-1 lists the SX registers and shows the state of
each register upon different reset.
Undefined
FFh
0Fh
Undefined
0Fh
Bits 0-4: Unde-
fined
Bits 5-7: 0
Bits 0-6: Unde-
fined
Bit 7: 1
FFh
Undefined
Undefined
Bits 0, 6-7: 1
Bits 1-5: Unde-
fined
Undefined
FFh
FFh
FFh
FFh
FFh
Undefined
Brown-out
Unchanged
FFh
0Fh
Unchanged
0Fh
Bits 0-2: Unde-
fined
Bits 3-4: (Note 1)
Bits 5-7: 0
Bits 0-6: Unde-
fined
Bit 7: 1
FFh
Unchanged
Unchanged
Bits 0, 6-7: 1
Bits 1-5: Unde-
fined
Unchanged
FFh
FFh
FFh
FFh
FFh
Unchanged
Watchdog
Timeout
Unchanged
FFh
0Fh
Unchanged
0Fh
Bits 0-2: Unde-
fined
Bits 3-4: (Note 2)
Bits 5-7: 0
Bits 0-6: Unde-
fined
Bit 7: 1
FFh
Unchanged
Unchanged
Bits 0, 6-7: 1
Bits 1-5: Unde-
fined
Unchanged
FFh
FFh
FFh
FFh
FFh
Unchanged
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