CY8C25122-24PI Cypress Semiconductor Corp, CY8C25122-24PI Datasheet - Page 115

• Manufacturer Part Number: CY8C25122-24PI
• Description: IC MCU 4K FLASH 256B 8-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C25xxxr

Specifications of CY8C25122-24PI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: CapSense
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Package Type: PDIP
• Screening Level: Industrial
• Pin Count: 8
• Mounting: Through Hole
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1424

Special Features of the CPU
interrupt will wake the part from sleep. The Stop bit in the
Status and Control Register (CPU_SCR) must be
cleared for a part to resume out of sleep.
CPU Running
Any digital PSoC block that is clocked by a System Clock
other than the 32K system-clocking signal or external
Analog
Run
Sleep
pins will be stopped, as these clocks do not run in sleep
mode.
The Internal Main Oscillator restarts immediately on exit-
ing either the Full Sleep or CPU Sleep modes. Analog
functions must be re-enabled by firmware. If the External
Crystal Oscillator is used and the internal PLL is
enabled, the PLL will take many cycles to change from
CPU Sleep
Full Sleep
its initial 2.5% accuracy to track that of the External Crys-
tal Oscillator. If the PLL is enabled, there will be a 30 µ s
(one full 32K cycle) delay hold-off time for the CPU to let
CPU not Running
the VCO and PLL stabilize. If the PLL is not enabled, the
hold-off time is one half of the 32K cycle. For further
Figure 31: Three Sleep States
details on PLL, see 7.0.
The Sleep interrupt allows the microcontroller to wake up
periodically and poll system components while maintain-
ing very low average power consumption. The sleep
interrupt may also be used to provide periodic interrupts
during non-sleep modes.
In System Sleep State, GPIO Pins P2[4] and P2[6]
should be held to a logic low or a false Low Voltage
Detect interrupt may be triggered. The cause is in the
System Sleep State, the internal Bandgap reference
generator is turned off and the reference voltage is main-
tained on a capacitor.
The circumstances are that during sleep, the reference
voltage on the capacitor is refreshed periodically at the
sleep system duty cycle. Between refresh cycles, this
voltage may leak slightly to either the positive supply or
ground. If pins P2[4] or P2[6] are in a high state, the leak-
age to the positive supply is accelerated (especially at
high temperature). Since the reference voltage is com-
pared to the supply to detect a low voltage condition, this
accelerated leakage to the positive supply voltage will
cause that voltage to appear lower than it actually is,
leading to the generation of a false Low Voltage Detect
interrupt.
September 5, 2002
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
115