CY8C25122-24PI Cypress Semiconductor Corp, CY8C25122-24PI Datasheet - Page 24

• Manufacturer Part Number: CY8C25122-24PI
• Description: IC MCU 4K FLASH 256B 8-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C25xxxr

Specifications of CY8C25122-24PI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: CapSense
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Package Type: PDIP
• Screening Level: Industrial
• Pin Count: 8
• Mounting: Through Hole
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1424

Examples :
2.3.8
The result of an instruction using this addressing mode is
placed within the RAM memory. Operand 1 is the
address of the result. Operand 2 is an address that
points to a location in the RAM memory that is the source
for the instruction. This addressing mode is only valid on
the MOV instruction. The instruction using this address-
ing mode is three bytes in length.
Table 20:
Example :
2.3.9
The result of an instruction using this addressing mode is
placed in the Accumulator. Operand 1 is an address
pointing to a location within the memory space, which
contains an address (the indirect address) for the source
of the instruction. The indirect address is incremented as
part of the instruction execution. This addressing mode
is only valid on the MVI instruction. The instruction using
this addressing mode is two bytes in length. See Sec-
tion 7. Instruction Set in PSoC Designer: Assembly
24
ADD
MOV
MOV
Instruction
Opcode
[7], [8]
[X+7],
REG[X+8], 6
Destination Direct Direct
Source Indirect Post Increment
Destination Direct Direct
Destination Address Source Address
Operand 1
;In this case, the value
;in the memory location at
;address 8 is moved to the
;memory location at
;address 7.
5
;In this case, the
;value in the memory
;location at address
;X+7 is added with
;the immediate value
;of 5, and the result
;is placed in the
;memory location at
;address X+7.
;In this case, the
;immediate value of 6
;is moved into the
;location in the
;register space at
;address X+8.
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
Operand 2
Language User Guide for further details on MVI instruc-
tion.
Table 21:
Example :
2.3.10 Destination Indirect Post Increment
The result of an instruction using this addressing mode is
placed within the memory space. Operand 1 is an
address pointing to a location within the memory space,
which contains an address (the indirect address) for the
destination of the instruction. The indirect address is
incremented as part of the instruction execution. The
source for the instruction is the Accumulator. This
addressing mode is only valid on the MVI instruction.
The instruction using this addressing mode is two bytes
in length.
Table 22:
Example :
MVI
MVI
Instruction
Instruction
Opcode
Opcode
A,
[8], A
Source Indirect Post Increment
Destination Indirect Post Increment
[8]
Source Address Address
Destination Address Address
;In this case, the value
;in the memory location at
;address 8 is an indirect
;address. The memory
;location pointed to by
;the indirect address is
;moved into the
;Accumulator. The
;indirect address is then
;incremented.
;In this case, the
;value in the memory
;location at address 8
;is an indirect
;address. The
;Accumulator is moved
;into the memory
;location pointed to by
;the indirect address.
;The indirect address
;is then incremented.
Operand 1
Operand 1
September 5, 2002