CY8C25122-24PI Cypress Semiconductor Corp, CY8C25122-24PI Datasheet - Page 61

• Manufacturer Part Number: CY8C25122-24PI
• Description: IC MCU 4K FLASH 256B 8-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C25xxxr

Specifications of CY8C25122-24PI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: CapSense
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.25V
• Package Type: PDIP
• Screening Level: Industrial
• Pin Count: 8
• Mounting: Through Hole
• Rad Hardened: No
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 428-1424

trigger capture operations that permit calculation of
elapsed “ticks.” Timer-configured PSoC blocks may be
chained to arbitrary lengths in 8 bit increments.
9.5.1.2
Data Register 1 establishes the period or integer clock
division value. Data Register 0 holds the current state of
the down counter. If the function is disabled, writing a
period into Data Register 1, will automatically load Data
Register 0. It is also automatically reloaded on the clock
cycle after it reaches zero, the terminal count value.
When a capture event occurs, the current value of Data
Register 0 is transferred to Data Register 2. The cap-
tured value in Data Register 2 may then be read by the
CPU. In addition to the hardware capture input, A CPU
read of Data Register 0 generates a software capture
event. This read will return 0 as data. A subsequent read
of Data Register 2 will return the captured value. Control
Register 0 contains one bit to enable/disable the func-
tion.
9.5.1.3
There are two inputs, the Source Clock and the Hard-
ware Capture signal. The down counter is decremented
on the rising-edge of the Source Clock. A hardware cap-
ture event is signaled by a rising edge of the Hardware
Capture signal. This is synchronized to the 24 MHz sys-
tem clock and the data is synchronously transferred to
Data Register 2. The Hardware Capture Signal is OR’ed
with a software capture signal that is generated when
Data Register 0 is read directly by the CPU. In order to
use the software capture mechanism, the Hardware
Capture signal input selection must be low. The multi-
plexers selecting these input sources are controlled by
the PSoC block Input Register (DBA00IN-DCA07IN).
9.5.1.4
The Terminal Count signal is the primary output and it
exhibits a duty cycle that is the reciprocal of the period
value contained in Data Register 1. In other words, it is
high during the source clock cycle when the value in
Data Register 0 is zero and low otherwise. The Terminal
Count can be routed to additional analog or digital PSoC
blocks or via Global Output lines. The auxiliary output is
the Compare True signal. This output is high when the
September 5, 2002
Registers
Inputs
Outputs
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
current count is less than (or less than or equal to) the
value in Data Register 2 (compare type controlled by
Mode[1] in the PSoC block Function Register). The auxil-
iary output can be routed via Global Output lines. The
PSoC block Output Register (DBA00OU-DCA07OU)
controls output options.
9.5.1.5
Interrupts may be generated in either of two ways. First,
the PSoC block may optionally generate an interrupt on
the rising edge of Terminal Count or the rising edge of
the Compare True signal. The selection of interrupt
source is determined by the MODE[0] bit of the PSoC
block Function Register (DBA00FN-DCA07FN). The
MODE[1] bit controls whether the comparison operation
is “less than” or “less than or equal to.” If capture events
are disabled, Data Register 2 can be used to create a
periodic interrupt with a particular offset from the terminal
count.
9.5.1.6
1.
2.
3.
Constraints
Hardware/software synchronous capture is only
available with a clocking rate of 24 MHz and below.
Software Capture
When a capture event occurs, all bytes in a multi-
byte timer transfer simultaneously from the current
count (Data Register 0) to the capture register (Data
Register 2). To generate a software capture event,
only the least significant Data Register 0 byte needs
to be read by the CPU. This causes the same simul-
taneous transfer as a hardware event.
Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Reg-
ister 0 (Counter) to initialize or reset the count. All
outputs are low and the block interrupt is held low.
Disabling a timer does not affect the current count
value and it may be read by the CPU. However,
since hardware/software capture is disabled in this
state, two reads are required to read each byte of a
multi-byte register. One to transfer each Data Regis-
ter 0 count value to the associated Data Register 2
capture register, then one to read the result in Data
Register 2.
Interrupts
Usage Notes
Digital PSoC Blocks
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