CY7C60223-PXC Cypress Semiconductor Corp, CY7C60223-PXC Datasheet - Page 7

• Manufacturer Part Number: CY7C60223-PXC
• Description: IC MCU 8K WIRELESS 24-DIP
• Manufacturer: Cypress Semiconductor Corp
• Series: enCoRe™ II CY7C602xxr

Specifications of CY7C60223-PXC

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: SPI
• Peripherals: LVD, POR, WDT
• Number Of I /o: 20
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 24-DIP (0.300", 7.62mm)
• For Use With: 770-1001 - ISP 4PORT CYPRESS ENCORE II MCUCY3216 - KIT PROGRAMMER MODULAR428-1774 - EXTENSION KIT FOR ENCORE II428-1773 - KIT DEVELOPMENT ENCORE II
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 428-1797

Table 7-1. enCoRe II LV Register Summary (continued)
The XIO bit in the CPU Flags Register must be set to access the extended register space for all registers above 0xFF.
Note In the R/W column:
Document 38-16016 Rev. *F
Addr
1E0
1E3
1EB
1E4
DA
DB
DC
DE
b = Both Read and Write
r = Read Only
w = Write Only
c = Read or Clear
d = Calibration Value. Must not change during normal use
3C
3D
DF
E1
E0
E2
E3
F7
FF
34
35
36
--
--
--
--
--
INT_MSK3
INT_MSK2
INT_MSK1
INT_MSK0 GPIO Port 1
LPOSCTR
INT_CLR0 GPIO Port 1 Sleep Timer
INT_CLR1
INT_CLR2
CPU_PCH
CPU_SCR
OSC_CR0
CPU_PCL
RESWDT
XOSCTR
SPIDATA
CPU_SP
ECO_TR
VLTCMP
IOSCTR
INT_VC
Name
CPU_A
CPU_X
CPU_F
LVDCR
SPICR
32 kHz Low
ENSWINT
Int Enable
Int Enable
Reserved
Reserved
Sleep Duty Cycle [1:0]
TCAP0
TCAP0
Power
Swap
GIES
7
Reserved
Reserved
Prog Interval
Prog Interval
GPIO Port 4 GPIO Port 3 GPIO Port 2
GPIO Port 4
Sleep Timer
Int Enable
Int Enable
Int Enable
foffset[2:0]
Reserved
Reserved
Reserved
LSB First
Reserved
Timer
Timer
6
GPIO Port 3
1 ms Timer
1 ms Timer
Int Enable
Int Enable
Int Enable
No Buzz
32 kHz Bias Trim [1:0]
WDRS
INT1
INT1
5
PORLEV[1:0]
Comm Mode
Reserved
GPIO Port 0
GPIO Port 2
GPIO Port 0
Int Enable
Int Enable
Reset Watchdog Timer [7:0]
Temporary Register T1 [7:0]
PORS
Program Counter [15:8]
Pending Interrupt [7:0]
Program Counter [7:0]
XIO
Sleep Timer [1:0]
4
Stack Pointer [7:0]
SPIData[7:0]
X[7:0]
XOSC XGM [2:0]
SPI Receive
SPI Receive
Int Enable
Reserved
Reserved
Reserved
Reserved
CPOL
Super
Sleep
3
Reserved
SPI Transmit
SPI Transmit
Reserved
Reserved
Gain[4:0]
Int Enable
Int Enable
Reserved
32 kHz Freq Trim [3:0]
CPHA
Carry
INT2
INT2
2
CPU Speed [2:0]
Int Enable
VM[2:0]
Reserved
Reserved
Wrap Int
Counter
Counter
Enable
16-bit
Wrap
16-bit
INT0
INT0
Zero
LVD
1
CY7C601xx, CY7C602xx
SCLK Select
Int Enable
Int Enable
POR/LVD
POR/LVD
Global IE
TCAP1
TCAP1
PPOR
Mode
Stop
0
wwwwwww
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
bbbbbbbb
b-bbbbbb
-bbb-bbb
-bbb-bbb
--bbbbbb
--bb-bbb
---bbb-b
---brbbb
bbb-----
bbb-----
r-ccb--b
bb------
r-------
--------
--------
--------
--------
--------
------rr
R/W
w
Default
000ddddd
000ddddd
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000000
00000010
00010100
00001000
00000000
00000000
00000000
d-dddddd
Page 7 of 68
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