MC68HC908GP32CFB Freescale Semiconductor, MC68HC908GP32CFB Datasheet - Page 299
MC68HC908GP32CFB
Manufacturer Part Number
MC68HC908GP32CFB
Description
IC MCU 8MHZ 32K FLASH 44-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC68HC908GP32CFB.pdf
(410 pages)
Specifications of MC68HC908GP32CFB
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
33
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFP
For Use With
M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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19.7.2 Stop Mode
MC68HC908GP32
MOTOROLA
NOTE:
NOTE:
•
MC68HC08GP32
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module outputs (CGMOUT and
CGMXCLK) in stop mode, stopping the CPU and peripherals. Stop
recovery time is selectable using the SSREC bit in the mask option
register (MOR). If SSREC is set, stop recovery is reduced from the
normal delay of 4096 CGMXCLK cycles down to 32. This is ideal for
applications using canned oscillators that do not require long startup
times from stop mode.
External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
A break interrupt during stop mode sets the SIM break stop/wait bit
(SBSW) in the SIM break status register (SBSR).
The SIM counter is held in reset from the execution of the STOP
instruction until the beginning of stop recovery. It is then used to time the
recovery period.
To minimize stop current, all pins configured as inputs should be driven
to a logic 1 or logic 0.
Note : Previous data can be operand data or the STOP opcode, depending
CPUSTOP
R/W
IAB
IDB
on the last instruction.
—
Rev. 6
System Integration Module (SIM)
STOP ADDR
Figure 19-18. Stop Mode Entry Timing
Figure 19-18
PREVIOUS DATA
STOP ADDR + 1
shows stop mode entry timing.
NEXT OPCODE
System Integration Module (SIM)
SAME
SAME
Low-Power Modes
Technical Data
SAME
SAME
297
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