MC68HC908GP32CFB Freescale Semiconductor, MC68HC908GP32CFB Datasheet - Page 319

• Manufacturer Part Number: MC68HC908GP32CFB
• Description: IC MCU 8MHZ 32K FLASH 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GP32CFB

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• For Use With: M68EVB908GP32 - BOARD EVALUATION FOR HC908GP32
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

MC68HC908GP32
MOTOROLA
•
MC68HC08GP32
interrupts share the same CPU interrupt vector.
not possible to enable MODF or OVRF individually to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
If the CPU SPRF interrupt is enabled and the OVRF interrupt is not,
watch for an overflow condition.
miss an overflow. The first part of
to read the SPSCR and SPDR to clear the SPRF without problems.
However, as illustrated by the second transmission example, the OVRF
bit can be set in between the time that SPSCR and SPDR are read.
In this case, an overflow can be missed easily. Since no more SPRF
interrupts can be generated until this OVRF is serviced, it is not obvious
that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the
SPSCR following the read of the SPDR. This ensures that the OVRF
was not set before the SPRF was cleared and that future transmissions
can set the SPRF bit.
avoid this second SPSCR read, enable the OVRF to the CPU by setting
the ERRIE bit.
SPSCR
OVRF
READ
READ
SPDR
SPRF
1
2
3
4
BYTE 1
Serial Peripheral Interface Module (SPI)
—
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
BYTE 2 SETS SPRF BIT.
Rev. 6
1
Figure 20-9. Missed Read of Overflow Condition
2
3
Figure 20-10
BYTE 2
4
Figure 20-9
Figure 20-9
illustrates this process. Generally, to
BYTE 3
5
5
6
7
8
Serial Peripheral Interface Module (SPI)
6
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
CPU READS BYTE 2 IN SPDR, CLEARING SPRF BIT,
BUT NOT OVRF BIT.
BYTE 4 FAILS TO SET SPRF BIT BECAUSE
OVRF BIT IS NOT CLEARED. BYTE 4 IS LOST.
7
shows how it is possible to
shows how it is possible
(See Figure
BYTE 4
8
Error Conditions
Technical Data
20-11.) It is
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