MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 42

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

6 Parallel Input/Output
PORTA —Port A Data
DDRA —Data Direction Register for Port A
DDA[7:0] —Data Direction for Port A
42
MOTOROLA
RESET:
RESET:
Alt. Pin
And/or:
Func.:
M68HC11 K-series MCUs have up to 62 input/output lines, depending on the operating mode. To en-
hance the I/O functions, the data bus of this microcontroller is nonmultiplexed. The following table is a
summary of the configuration and features of each port.
Port C
Port D
Port G
Port H
Port A
Port B
Port E
Port F
Port
0 = Corresponding pin configured for input
1 = Corresponding pin configured for output
DDA7
Bit 7
OC1
Bit 7
PA7
PAI
0
I
Port pin function is mode dependent. Do not confuse pin function with the electrical
state of the pin at reset. Port pins are either driven to a specified logic level or are
configured as high impedance inputs. I/O pins configured as high-impedance in-
puts have port data that is indeterminate. The contents of the corresponding latch-
es are dependent upon the electrical state of the pins during reset. In port
descriptions, an "I" indicates this condition. Port pins that are driven to a known log-
ic level during reset are shown with a value of either one or zero. Some control bits
are unaffected by reset. Reset states for these bits are indicated with a "U".
To enable PA3 as fourth input capture, set the I4/O5 bit in the PACTL register. Oth-
erwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being
cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled,
writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5
has no effect when the TI4/O5 register is acting as IC4. PA7 drives the pulse ac-
cumulator input but also can be configured for general-purpose I/O or output com-
pare. Note that even when PA7 is configured as an output, the pin still drives the
pulse accumulator input.
Input Pins
DDA6
OC2
OC1
PA6
—
—
—
—
—
—
—
8
6
6
0
I
Freescale Semiconductor, Inc.
For More Information On This Product,
DDA5
OC3
OC1
PA5
Output Pins
5
5
0
I
Go to: www.freescale.com
—
—
—
—
—
—
—
—
DDA4
OC4
OC1
PA4
4
4
0
I
NOTE
NOTE
Bidirectional Pins
IC4/OC5
DDA3
OC1
PA3
3
3
0
I
—
8
8
8
6
8
8
8
DDA2
PA2
IC1
—
2
2
0
I
DDA1
PA1
IC2
—
1
1
0
I
High Order Address
Low Order Address
Memory Expansion
Shared Functions
PWM, Chip Select
A/D Converter
SCI and SPI
Data Bus
Timer
M68HC11 K Series
DDA0
$0000
$0001
MC68HC11KTS/D
Bit 0
Bit 0
PA0
IC3
—
0
I