MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 54

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MC68HC711K4CFU4

Manufacturer Part Number
MC68HC711K4CFU4
Description
IC MCU 24K 4MHZ EEPROM 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC11r
Datasheets

Specifications of MC68HC711K4CFU4

Core Processor
HC11
Core Size
8-Bit
Speed
4MHz
Connectivity
SCI, SPI
Peripherals
POR, PWM, WDT
Number Of I /o
62
Program Memory Size
24KB (24K x 8)
Program Memory Type
OTP
Eeprom Size
640 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68HC711K4CFU4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
RE —Receiver Enable
RWU —Receiver Wakeup Control
SBK —Send Break
SCSR1 —SCI Status Register 1
TDRE —Transmit Data Register Empty Flag
TC —Transmit Complete Flag
RDRF —Receive Data Register Full Flag
IDLE —Idle Line Detected Flag
OR —Overrun Error Flag
NF —Noise Error Flag
FE —Framing Error
54
MOTOROLA
RESET:
This flag is set when SCDR is empty. Clear the TDRE flag by reading SCSR1 and then writing to SCDR.
This flag is set when the transmitter is idle (no data, preamble, or break transmission in progress). Clear
the TC flag by reading SCSR1 and then writing to SCDR.
RDRF is set if a received character is ready to be read from SCDR. Clear the RDRF flag by reading
SCSR1 and then reading SCDR.
This flag is set if the RxD line is idle. Once cleared, IDLE is not set again until the RxD line has been
active and becomes idle again. The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1
and then reading SCDR.
OR is set if a new character is received before a previously received character is read from SCDR. Clear
the OR flag by reading SCSR1 and then reading SCDR.
NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading
SCSR1 and then reading SCDR.
FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR1
and then reading SCDR.
0 = Receiver disabled
1 = Receiver enabled
0 = Normal SCI receiver
1 = Wakeup enabled and receiver interrupts inhibited
0 = Break generator off
1 = Break codes generated as long as SBK = 1
0 = SCDR busy
1 = SCDR empty
0 = Transmitter busy
1 = Transmitter idle
0 = SCDR empty
1 = SCDR full
0 = RxD line is active
1 = RxD line is idle
0 = No overrun
1 = Overrun detected
0 = Unanimous decision
1 = Noise detected
0 = Stop bit detected
1 = Zero detected
TDRE
Bit 7
1
TC
6
1
Freescale Semiconductor, Inc.
For More Information On This Product,
RDRF
5
0
Go to: www.freescale.com
IDLE
4
0
OR
0
3
NF
2
0
FE
1
0
M68HC11 K Series
$0074
MC68HC11KTS/D
Bit 0
PF
0

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