MC68HC711K4CFU4 Freescale Semiconductor, MC68HC711K4CFU4 Datasheet - Page 61

• Manufacturer Part Number: MC68HC711K4CFU4
• Description: IC MCU 24K 4MHZ EEPROM 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC711K4CFU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 62
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: OTP
• Eeprom Size: 640 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

M68HC11 K Series
MC68HC11KTS/D
E CLOCK
WRITE
ADCTL
A multiplexer allows the single A/D converter to select one of 16 analog input signals.
The A/D converter control logic implements automatic conversion sequences on a selected channel
four times or on four channels once each. A write to the ADCTL register initiates conversions and, if
made while a conversion is in progress, a write to ADCTL also halts that conversion operation, sets
CCF, and proceeds to the next instruction.
When the SCAN bit is zero, four requested conversions are performed, once each, to fill the four result
registers. When SCAN is one, conversions continue in a round-robin fashion with the result registers
being updated as new data becomes available. When the MULT bit is zero, the A/D converter system
is configured to perform conversions on each channel in the group of four channels specified by the CD
and CC channel select bits.
TO
0
AND UPDATE ADDR1
ANALOG
INPUT
CONVERT FIRST
PIN
CHANNEL
SAMPLE ANALOG INPUT
Figure 15 Timing Diagram for a Sequence of Four A/D Conversions
Figure 16 Electrical Model of an Analog Input Pin (Sample Mode)
12 E CYCLES
Freescale Semiconductor, Inc.
< 2 pF
*
32
PROTECTION
This analog switch is closed only during the 12-cycle sample time.
For More Information On This Product,
DEVICE
INPUT
AND UPDATE ADDR2
CONVERT SECOND
+
–
CHANNEL
~
~
20 V
0.7 V
Go to: www.freescale.com
CYCLES
MSB
4
SUCCESSIVE APPROXIMATION SEQUENCE
64
BIT 6
CYC
2
AND UPDATE ADDR3
JUNCTION
LEAKAGE
CONVERT THIRD
DIFFUSION AND
POLY COUPLER
400 nA
BIT 5
CYC
CHANNEL
2
4 k
BIT 4
CYC
2
BIT 3
CYC
2
96
BIT 2
CYC
2
AND UPDATE ADDR4
CONVERT FOURTH
*
BIT 1
CYC
CHANNEL
2
V RL
~
CAPACITANCE
CYC
LSB
20 pF
2
DAC
CYC
END
FLAG
2
SET
CCF
MOTOROLA
128
SEQUENCE
SCAN = 1
REPEAT
CYCLES
IF
E
61