MC68HC908SR12CFA Freescale Semiconductor, MC68HC908SR12CFA Datasheet - Page 75

• Manufacturer Part Number: MC68HC908SR12CFA
• Description: MICROCONTROLLER 48 PIN
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908SR12CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, Temp Sensor
• Number Of I /o: 31
• Program Memory Size: 12KB (12K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 14x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: Q1145673

5.4 Configuration Register 1 (CONFIG1)
MC68HC908SR12•MC68HC08SR12 — Rev. 5.0
Freescale Semiconductor Configuration and Mask Option Registers (CONFIG & MOR)
NOTE:
Address:
The options except LVI5OR3 are one-time writable by the user after
each reset. The LVI5OR3 bit is one-time writable by the user only after
each POR (power-on reset). The CONFIG registers are not in the
FLASH memory but are special registers containing one-time writable
latches after each reset. Upon a reset, the CONFIG registers default to
predetermined settings as shown in
The mask option register (MOR) is used for selecting one of the three
clock options for the MCU. The MOR is a byte located in FLASH
memory, and is written to by a FLASH programming routine.
COPRS — COP Rate Select
LVISTOP — LVI Enable in Stop Mode
Reset:
Read:
Write:
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 21. Computer Operating Properly
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 22. Low-Voltage Inhibit
1 = COP time out period = 2
0 = COP time out period = 2
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
* Reset by POR only.
COPRS
$001F
Bit 7
Figure 5-2. Configuration Register 1 (CONFIG1)
0
LVISTOP LVIRSTD LVIPWRD LVI5OR3
6
0
Configuration and Mask Option Registers (CONFIG & MOR)
5
0
13
18
4
0
Figure 5-2
– 2
– 2
(LVI).)
4
4
Configuration Register 1 (CONFIG1)
ICLK cycles
ICLK cycles
0*
3
and
(COP).)
SSREC
2
0
Figure
STOP
1
0
5-3.
Data Sheet
COPD
Bit 0
0
75