MC68HC908GR8CP Freescale Semiconductor, MC68HC908GR8CP Datasheet - Page 121

• Manufacturer Part Number: MC68HC908GR8CP
• Description: IC MCU FLASH 8BIT 8MHZ 4K 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GR8CP

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 17
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

7.6.5 PLL VCO Range Select Register
MC68HC908GR8 — Rev 4.0
MOTOROLA
NOTE:
NOTE:
Address:
PMRS may be called PVRS on other HC08 derivatives.
The PLL VCO range select register (PMRS) contains the programming
information required for the hardware configuration of the VCO.
VRS7–VRS0 — VCO Range Select Bits
The VCO range select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
These read/write bits control the hardware center-of-range linear
multiplier L which, in conjunction with E (see
Programming the
hardware center-of-range frequency, f
written when the PLLON bit in the PCTL is set. (See
Programming
register disables the PLL and clears the BCS bit in the PLL control
register (PCTL). (See
Programming
default range multiply value of 64.
For More Information On This Product,
Figure 7-8. PLL VCO Range Select Register (PMRS)
$003A
VRS7
Bit 7
0
Clock Generator Module (CGMC)
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VRS6
Exceptions.) A value of $00 in the VCO range select
Exceptions.). Reset initializes the register to $40 for a
6
1
PLL, and
VRS5
Base Clock Selector Circuit
5
0
PLL Control
VRS4
4
0
VRS
VRS3
3
0
Register), controls the
Clock Generator Module (CGMC)
. VRS7–VRS0 cannot be
PLL
VRS2
2
0
Circuits,
and
Special
CGMC Registers
VRS1
Special
1
0
Technical Data
VRS0
Bit 0
0
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