MC68HC908GR8CP Freescale Semiconductor, MC68HC908GR8CP Datasheet - Page 253
MC68HC908GR8CP
Manufacturer Part Number
MC68HC908GR8CP
Description
IC MCU FLASH 8BIT 8MHZ 4K 28-DIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Specifications of MC68HC908GR8CP
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
17
Program Memory Size
7.5KB (7.5K x 8)
Program Memory Type
FLASH
Ram Size
384 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 6x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer:
FSC
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MC68HC908GR8 — Rev 4.0
MOTOROLA
NOTE:
Address:
LOOPS — Loop Mode Select Bit
ENSCI — Enable SCI Bit
TXINV — Transmit Inversion Bit
Setting the TXINV bit inverts all transmitted values, including idle, break,
start, and stop bits.
M — Mode (Character Length) Bit
Reset:
Read:
Write:
Freescale Semiconductor, Inc.
This read/write bit enables loop mode operation. In loop mode the
PE1/RxD pin is disconnected from the SCI, and the transmitter output
goes into the receiver input. Both the transmitter and the receiver
must be enabled to use loop mode. Reset clears the LOOPS bit.
This read/write bit enables the SCI and the SCI baud rate generator.
Clearing ENSCI sets the SCTE and TC bits in SCI status register 1
and disables transmitter interrupts. Reset clears the ENSCI bit.
This read/write bit reverses the polarity of transmitted data. Reset
clears the TXINV bit.
This read/write bit determines whether SCI characters are eight or
nine bits long. See
stop bit, as a receiver wakeup signal, or as a parity bit. Reset clears
the M bit.
For More Information On This Product,
1 = Loop mode enabled
0 = Normal operation enabled
1 = SCI enabled
0 = SCI disabled
1 = Transmitter output inverted
0 = Transmitter output not inverted
LOOPS
Serial Communications Interface (SCI)
$0013
Bit 7
0
Figure 18-9. SCI Control Register 1 (SCC1)
Go to: www.freescale.com
ENSCI
6
0
Table
TXINV
5
0
18-5. The ninth bit can serve as an extra
M
4
0
Serial Communications Interface (SCI)
WAKE
3
0
ILTY
2
0
PEN
1
0
Technical Data
I/O Registers
Bit 0
PTY
0
253
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