MC68HC908LK24CFQ Freescale Semiconductor, MC68HC908LK24CFQ Datasheet - Page 236
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MC68HC908LK24CFQ
Manufacturer Part Number
MC68HC908LK24CFQ
Description
IC MCU 24K FLASH 8MHZ SPI 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MC68HC908LK24CFQ
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LK24CFQ
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC908LK24CFQ
Manufacturer:
FRE/MOT
Quantity:
20 000
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Real Time Clock (RTC)
Data Sheet
236
NOTE:
With compensation enabled, the RTC clock and calendar register
updates may not be synchronized to the timebase and chronograph
clocks, since their clocks are derived from the uncompensated
CGMXCLK.
Hence, time intervals for timebase ticks may not align with the RTC clock
and calendar register updates.
CHRCLR — Chronograph counter clear
CHRE — Chronograph Enable
RTCE — Real Time Clock Enable
TBH — Timebase High Frequency Select
Setting this write-only bit resets the chronograph counter and the
chronograph data register (CHRR). Setting CHRCLR has no effect on
any other registers. Counting resumes from $00. CHRCLR is cleared
automatically after the chronograph counter is reset and always reads
as logic 0. Reset clears the CHRCLR bit.
This read/write bit enables the chronograph counter. When the
chronograph counter is disabled (CHRE = 0), the value in the
chronograph data register is held at the count value. Reset clears the
CHRE bit.
This read/write bit enables the entire RTC module, allowing all RTC
and chronograph operations. Disabling the RTC module does not
affect the contents in the RTC registers. Reset clears the RTCE bit.
This read/write bit selects the timebase interrupt period for TB1 and
TB2. Reset clears the TBH bit.
1 = Chronograph counter cleared
0 = No effect
1 = Chronograph counter enabled
0 = Chronograph counter disabled
1 = RTC module enabled
0 = RTC module disabled
1 = TB1 interrupt is 0.125s; TB2 interrupt is 0.0625s
0 = TB1 interrupt is 0.5s; TB2 interrupt is 0.25s
Real Time Clock (RTC)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
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