MC68HC908LK24CFQ Freescale Semiconductor, MC68HC908LK24CFQ Datasheet - Page 83
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MC68HC908LK24CFQ
Manufacturer Part Number
MC68HC908LK24CFQ
Description
IC MCU 24K FLASH 8MHZ SPI 80-QFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908LK24CFUE.pdf
(464 pages)
Specifications of MC68HC908LK24CFQ
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, IRSCI, SPI
Peripherals
LCD, LVD, POR, PWM
Number Of I /o
40
Program Memory Size
24KB (24K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68HC908LK24CFQ
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC68HC908LK24CFQ
Manufacturer:
FRE/MOT
Quantity:
20 000
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MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
PEE — Port E Enable
STOP_IRCDIS — Internal RC Oscillator Stop Mode Disable
STOP_XCLKEN — Crystal Oscillator Stop Mode Enable
DIV2CLK — Divide-by-2 Clock Bypass
Setting PEE configures the PTE0/FP11–PTE7/FP18 pins for LCD
frontplane driver use. Reset clears this bit.
Setting STOP_IRCDIS disables the internal RC oscillator during stop
mode. When this bit is cleared, the internal RC oscillator continues to
operate in stop mode. Reset clears this bit.
Setting STOP_XCLKEN enables the external crystal (XTAL) oscillator
to continue operating in stop mode. This is useful for driving the real
time clock module to allow it to generate periodic wake up while in
stop mode. When this bit is cleared, the external XTAL oscillator will
be disabled during stop mode. Reset clears this bit.
When CGMXCLK is selected to drive the system clocks (BCS=0),
setting DIV2CLK allows the CGMXCLK to bypass the divide-by-2
divider in the CGM module; CGMOUT will equal CGMXCLK and bus
clock will equal CGMXCLK divide-by-2.
DIV2CLK bit has no effect when the BCS=1 in the PLL control
register (CGMVCLK selected and divide-by-2 always enabled). Reset
clears this bit.
1 = PTE0/FP11–PTE7/FP18 pins configured as LCD frontplane
0 = PTE0/FP11–PTE7/FP18 pins configured as standard I/O pins:
1 = Internal RC oscillator disabled during stop mode
0 = Internal RC oscillator enabled during stop mode
1 = XTAL oscillator enabled during stop mode
0 = XTAL oscillator disabled during stop mode
1 = Divide-by-2 divider bypassed;
0 = Divide-by-2 divider enabled;
Configuration Registers (CONFIG)
driver pins: FP11–FP18
PTE0–PTE7
When BSC=0, CGMOUT equals CGMXCLK
When BSC=0, CGMOUT equals CGMXCLK divide-by-2
Configuration Register 2 (CONFIG2)
Configuration Registers (CONFIG)
Data Sheet
83
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