MC9S08GT60CFB Freescale Semiconductor, MC9S08GT60CFB Datasheet - Page 217

• Manufacturer Part Number: MC9S08GT60CFB
• Description: IC MCU 60K FLASH 20MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFB

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SRW — Slave Read/Write
IICIF — IIC Interrupt Flag
RXAK — Receive Acknowledge
13.5.5
DATA — Data
Freescale Semiconductor
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When addressed as a slave the SRW bit indicates the value of the R/W command bit of the calling
address sent to the master.
The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by writing a
one to it in the interrupt routine. One of the following events can set the IICIF bit:
When the RXAK bit is low, it indicates an acknowledge signal has been received after the completion
of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
In master transmit mode, when data is written to the IIC1D, a data transfer is initiated. The most
significant bit is sent first. In master receive mode, reading this register initiates receiving of the next
byte of data.
In slave mode, the same functions are available after an address match has occurred.
1 = Slave transmit, master reading from slave.
0 = Slave receive, master writing to slave.
One byte transfer completes
Match of slave address to calling address
Arbitration lost
1 = Interrupt pending.
0 = No interrupt pending.
1 = No acknowledge received.
0 = Acknowledge received.
IIC Data I/O Register (IIC1D)
When transitioning out of master receive mode, the IIC mode should be
switched before reading the IIC1D register to prevent an inadvertent
initiation of a master receive data transfer.
Reset:
Read:
Write:
Bit 7
0
Figure 13-9. IIC Data I/O Register (IIC1D)
MC9S08GB/GT Data Sheet, Rev. 2.3
6
0
5
0
NOTE
4
0
DATA
3
0
2
0
Inter-Integrated Circuit (IIC) Module
1
0
Bit 0
0
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