MC9S08GT60CFB Freescale Semiconductor, MC9S08GT60CFB Datasheet - Page 75

• Manufacturer Part Number: MC9S08GT60CFB
• Description: IC MCU 60K FLASH 20MHZ 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT60CFB

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

LVDRE — Low-Voltage Detect Reset Enable
LVDSE — Low-Voltage Detect Stop Enable
LVDE — Low-Voltage Detect Enable
5.8.8
This register is used to report the status of the low voltage warning function, and to configure the stop mode
behavior of the MCU.
LVWF — Low-Voltage Warning Flag
LVWACK — Low-Voltage Warning Acknowledge
Freescale Semiconductor
This read/write bit enables LVDF events to generate a hardware reset (provided LVDE = 1).
Provided LVDE = 1, this read/write bit determines whether the low-voltage detect function operates
when the MCU is in stop mode.
This read/write bit enables low-voltage detect logic and qualifies the operation of other bits in this
register.
1
The LVWF bit indicates the low-voltage warning status.
The LVWACK bit indicates the low-voltage warning acknowledge.
Writing a 1 to LVWACK clears LVWF to 0 if a low voltage warning is not present.
V
LVWF will be set in the case when V
1 = Force an MCU reset when LVDF = 1.
0 = LVDF does not generate hardware resets.
1 = Low-voltage detect enabled during stop mode.
0 = Low-voltage detect disabled during stop mode.
1 = LVD logic enabled.
0 = LVD logic disabled.
1 = Low voltage warning is present or was present.
0 = Low voltage warning not present.
LVW
.
System Power Management Status and Control 2 Register (SPMSC2)
Figure 5-9. System Power Management Status and Control 2 Register (SPMSC2)
Power-on reset:
Any other reset:
LVD reset:
Read:
Write:
LVWF
Bit 7
0
0
0
(1)
(1)
1
Supply
= Unimplemented or Reserved
LVWACK
MC9S08GB/GT Data Sheet, Rev. 2.3
6
0
0
0
0
transitions below the trip point or after reset and V
LVDV
0
U
U
5
Reset, Interrupt, and System Control Registers and Control Bits
LVWV
0
U
U
4
PPDF
3
0
0
0
U = Unaffected by reset
PPDACK
0
2
0
0
0
Supply
PDC
1
0
0
0
is already below
PPDC
Bit 0
0
0
0
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