HD64F2134FA20 Renesas Electronics America, HD64F2134FA20 Datasheet - Page 220
HD64F2134FA20
Manufacturer Part Number
HD64F2134FA20
Description
IC H8S MCU FLASH 128K 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Specifications of HD64F2134FA20
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number:
HD64F2134FA20
Manufacturer:
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Quantity:
10 000
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HD64F2134FA20V
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Section 7 Data Transfer Controller [H8S/2138 Group]
7.2.2
MRB is an 8-bit register that controls the DTC operating mode.
Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. In chain transfer,
multiple data transfers can be performed consecutively in response to a single transfer request.
With data transfer for which CHNE is set to 1, there is no determination of the end of the specified
number of transfers, clearing of the interrupt source flag, or clearing of DTCER.
Bit 7
CHNE
0
1
Bit 6—DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are
disabled or enabled after a data transfer.
Bit 6
DISEL
0
1
Bits 5 to 0—Reserved: In the H8S/2138 Group these bits have no effect on DTC operation, and
should always be written with 0.
Rev. 4.00 Jun 06, 2006 page 164 of 1004
REJ09B0301-0400
Bit
Initial value
Read/Write
DTC Mode Register B (MRB)
Description
End of DTC data transfer (activation waiting state is entered)
DTC chain transfer (new register information is read, then data is transferred)
Description
After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is
0 (the DTC clears the interrupt source flag of the activating interrupt to 0)
After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the
interrupt source flag of the activating interrupt to 0)
CHNE
Unde-
fined
—
7
DISEL
Unde-
fined
—
6
Unde-
fined
—
—
5
Unde-
fined
—
—
4
Unde-
fined
—
—
3
Unde-
fined
—
—
2
Unde-
fined
—
—
1
Unde-
fined
—
—
0
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