HD64F3664FY Renesas Electronics America, HD64F3664FY Datasheet - Page 230

• Manufacturer Part Number: HD64F3664FY
• Description: IC H8 MCU FLASH 32K 48QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3664FY

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SCI
• Peripherals: PWM, WDT
• Number Of I /o: 29
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 48-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Section 14 Serial Communication Interface 3 (SCI3)
14.3.4
TDR is an 8-bit register that stores data for transmission. When the SCI3 detects that TSR is
empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-
buffered structure of TDR and TSR enables continuous serial transmission. If the next transmit
data has already been written to TDR during transmission of one-frame data, the SCI3 transfers
the written data to TSR to continue transmission. To achieve reliable serial transmission, write
transmit data to TDR only once after confirming that the TDRE bit in SSR is set to 1. TDR is
initialized to H'FF.
14.3.5
SMR is used to set the SCI3’s serial transfer format and select the on-chip baud rate generator
clock source.
Rev. 6.00 Mar. 24, 2006 Page 200 of 412
REJ09B0142-0600
Bit
7
6
5
4
Transmit Data Register (TDR)
Serial Mode Register (SMR)
Bit Name
COM
CHR
PE
PM
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
Parity Enable (enabled only in asynchronous mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity bit is
checked in reception.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.