HD64F3664FY Renesas Electronics America, HD64F3664FY Datasheet - Page 25
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HD64F3664FY
Manufacturer Part Number
HD64F3664FY
Description
IC H8 MCU FLASH 32K 48QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.US3664-BAG1.pdf
(446 pages)
Specifications of HD64F3664FY
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
48-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F3664FYV
Manufacturer:
RENE
Quantity:
5 325
Company:
Part Number:
HD64F3664FYV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 15.6 Master Receive Mode Operation Timing Example (1)
Figure 15.6 Master Receive Mode Operation Timing Example (2)
Figure 15.7 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0) ....... 256
Figure 15.8 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0) ....... 257
Figure 15.9 Example of Slave Transmit Mode Operation Timing (MLS = 0) .......................... 259
Figure 15.10 I
Figure 15.11 IRIC Setting Timing and SCL Control.................................................................. 260
Figure 15.12 Block Diagram of Noise Canceler......................................................................... 261
Figure 15.13 Sample Flowchart for Master Transmit Mode....................................................... 262
Figure 15.14 Sample Flowchart for Master Receive Mode ........................................................ 263
Figure 15.15 Sample Flowchart for Slave Receive Mode .......................................................... 264
Figure 15.16 Sample Flowchart for Slave Transmit Mode......................................................... 265
Figure 15.17 Flowchart and Timing of Start Condition Instruction Issuance
Figure 15.18 IRIC Flag Clear Timing on WAIT Operation ....................................................... 271
Figure 15.19 Notes on ICDR Reading with TRS = 1 Setting in Master Mode........................... 272
Figure 15.20 Notes on ICDR Writing with TRS = 0 Setting in Slave Mode.............................. 273
Section 16 A/D Converter
Figure 16.1 Block Diagram of A/D Converter ........................................................................... 276
Figure 16.2 A/D Conversion Timing .......................................................................................... 282
Figure 16.3 External Trigger Input Timing ................................................................................ 283
Figure 16.4 A/D Conversion Accuracy Definitions (1) .............................................................. 285
Figure 16.5 A/D Conversion Accuracy Definitions (2) .............................................................. 285
Figure 16.6 Analog Input Circuit Example................................................................................. 286
Section 17 EEPROM
Figure 17.1 Block Diagram of EEPROM ................................................................................... 288
Figure 17.2 EEPROM Bus Format and Bus Timing .................................................................. 290
Figure 17.3 Byte Write Operation .............................................................................................. 293
Figure 17.4 Page Write Operation .............................................................................................. 294
Figure 17.5 Current Address Read Operation............................................................................. 295
Figure 17.6 Random Address Read Operation ........................................................................... 296
Figure 17.7 Sequential Read Operation (when current address read is used)............................. 297
Section 18 Power Supply Circuit
Figure 18.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 299
Figure 18.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 300
(MLS = ACKB = 0, WAIT = 1) ............................................................................. 254
(MLS = ACKB = 0, WAIT = 1) ............................................................................. 255
for Retransmission ................................................................................................ 270
2
C Bus Data Format (Serial Format) .................................................................... 259
Rev. 6.00 Mar. 24, 2006 Page xxiii of xxviii
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