HD64F3664FY Renesas Electronics America, HD64F3664FY Datasheet - Page 272
![IC H8 MCU FLASH 32K 48QFP](/photos/28/61/286105/48-lqfp__plqp0048kc-a_sml.jpg)
HD64F3664FY
Manufacturer Part Number
HD64F3664FY
Description
IC H8 MCU FLASH 32K 48QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300H Tinyr
Datasheet
1.US3664-BAG1.pdf
(446 pages)
Specifications of HD64F3664FY
Core Processor
H8/300H
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SCI
Peripherals
PWM, WDT
Number Of I /o
29
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
48-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
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Manufacturer
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Section 15 I
15.3.5
I
interface.
Rev. 6.00 Mar. 24, 2006 Page 242 of 412
REJ09B0142-0600
Bit
7
6
5
4
2
C bus control register (ICCR) consists of the control bits and interrupt request flags of I
I
2
Bit Name
ICE
IEIC
MST
TRS
2
C Bus Control Register (ICCR)
C Bus Interface (IIC)
Initial
Value
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
I
When this bit is set to 1, the I
enabled to send/receive data and drive the bus since it
is connected to the SCL and SDA pins. ICMR and
ICDR can be accessed.
When this bit is cleared, the module is halted and
separated from the SCL and SDA pins. SAR and SARX
can be accessed.
I
When this bit is 1, Interrupts are enabled by IRIC.
Master/Slave Select
Transmit/Receive Select
00: Slave receive mode
01: Slave transmit mode
10: Master receive mode
11: Master transmit mode
Both these bits will be cleared by hardware when they
lose in a bus contention in master mode of the I
format. In slave receive mode, the R/W bit in the first
frame immediately after the start automatically sets
these bits in receive mode or transmit mode by using
hardware. The settings can be made again for the bits
that were set/cleared by hardware, by reading these
bits. When the TRS bit is intended to change during a
transfer, the bit will not be switched until the frame
transfer is completed, including acknowledgement.
2
2
C Bus Interface Enable
C Bus Interface Interrupt Enable
2
C bus interface module is
2
C bus
2
C bus
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