M30803FGFP#D3 Renesas Electronics America, M30803FGFP#D3 Datasheet - Page 100
M30803FGFP#D3
Manufacturer Part Number
M30803FGFP#D3
Description
IC M16C MCU FLASH 256K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet
1.M30803FGGPU3.pdf
(360 pages)
Specifications of M30803FGFP#D3
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M
R
R
e
E
1
v
J
6
Figure 11.6 Example of the transfer cycles for a source read
1 .
0
C
9
0 .
8 /
B
(1) •When 8-bit data is transferred
(4) •When one wait is inserted into the source read under the conditions in (2)
(2) •When 16-bit data is transferred and the source address is odd
(3) •When one wait is inserted into the source read under the conditions in (1)
0
0
0
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
BCLK
Address
bus
RD signal
WR signal
Data
bus
1
•When 16-bit data is transferred on a 16-bit data bus and the source address is even
A
•When 16-bit data is transferred and the width of data bus at the source is 8-bit
(When the width of data bus at the destination is 8-bit, there are also two destination write cycles).
(When 16-bit data is transferred and the width of data but at the destination is 8-bit, there are
G
Note: The same timing changes occur with the respective conditions at the destination as at the source.
8
two destination write cycles).
u
7
o r
. g
0 -
u
1
0
p
0
, 2
0
2
0
0
CPU use
CPU use
CPU use
5
CPU use
CPU use
Page 87
CPU use
CPU use
CPU use
f o
Source
Source
3
2
9
Source
Source
Source
Source
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Destination
Source + 1
Destination
Destination
Source + 1
Destination
CPU use
CPU use
Destination
CPU use
CPU use
CPU use
CPU use
CPU use
CPU use
11. DMAC
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