M30803FGFP#D3 Renesas Electronics America, M30803FGFP#D3 Datasheet - Page 80
M30803FGFP#D3
Manufacturer Part Number
M30803FGFP#D3
Description
IC M16C MCU FLASH 256K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet
1.M30803FGGPU3.pdf
(360 pages)
Specifications of M30803FGFP#D3
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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Table 9.6 Interrupt Sequence Execution Time
Note 1: Allocate interrupt vector addresses in even addresses, if possible.
Note 2: The vector table is fixed to even address.
Note 3: The high-speed interrupt is independent of these conditions.
6
1 .
_______
Peripheral I/O
INT instruction
NMI
Watchdog timer
Undefined instruction
Address match
Overflow
BRK instruction (Variable vector table)
Single step
BRK2 instruction
BRK instruction (Fixed vector table)
High-speed interrupt (Note 3)
0
C
9
0 .
Time (a) varies with each instruction being executed. The DIVX instruction requires a maximum time that
consists of 24* cycles.
Time (b) is shown in Table 9.6.
8 /
B
0
0
0
1
A
G
8
u
7
o r
. g
0 -
* It is when the divisor is immediate or register. When the divisor is memory, the following value is
u
added.
X is number of wait of the divisor area. Y is number of wait of the indirect address stored area.
When X and Y are in odd address or in 8 bits bus area, double the value of X and Y.
1
0
p
0
, 2
0
2
• Normal addressing
• Index addressing
• Indirect addressing
• Indirect index addressing
0
0
Interrupt
5
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9
Interrupt vector address
Even address (Note 2)
Even address (Note 2)
Even address (Note 2)
Vector table is internal
Odd address (Note 1)
Odd address (Note 1)
Odd address (Note 1)
: 2 + X
: 3 + X
: 5 + X + 2Y
: 6 + X + 2Y
Even address
Even address
Even address
register
16 bits data bus
14 cycles
16 cycles
12 cycles
14 cycles
13 cycles
14 cycles
17 cycles
19 cycles
19 cycles
5 cycles
9. Interrupt Outline
8 bits data bus
16 cycles
16 cycles
14 cycles
14 cycles
15 cycles
16 cycles
19 cycles
19 cycles
21 cycles
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