M30803FGFP#D3 Renesas Electronics America, M30803FGFP#D3 Datasheet - Page 199
M30803FGFP#D3
Manufacturer Part Number
M30803FGFP#D3
Description
IC M16C MCU FLASH 256K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet
1.M30803FGGPU3.pdf
(360 pages)
Specifications of M30803FGFP#D3
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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8 /
B
The DRAM self-refresh operates in STOP mode, etc.
When shifting to self-refresh, select DRAM ignored by the DRAM space select bit. In the next instruction,
simultaneously set the DRAM space select bit and self-refresh ON by self-refresh mode bit. Also, insert
two NOPs after the instruction that sets the self-refresh mode bit to "1".
Do not access external memory while operating in self-refresh. (All external memory space access is
inhibited. )
When disabling self-refresh, simultaneously select DRAM ignored by the DRAM space select bit and self-
refresh OFF by self-refresh mode bit. In the next instruction, set the DRAM space select bit.
Do not access the DRAM space immediately after setting the DRAM space select bit.
Example) One wait is selected by the wait select bit and 4MB is selected by the DRAM space select bit
Figures 25.4 to 25.6 show the bus timing during DRAM access.
0
0
0
1
A
8
G
u
7
o r
. g
0 -
Shifting to self-refresh
Disable self-refresh
u
1
0
p
0
, 2
0
2
0
•••
mov.b
mov.b
nop
nop
•••
•••
mov.b
mov.b
nop
nop
•••
0
5
Page 186
#00000001b,DRAMCONT
#10001011b,DRAMCONT
#00000001b,DRAMCONT
#00001011b,DRAMCONT
f o
3
2
9
;DRAM ignored, one wait is selected
;Set self-refresh, select 4MB and one wait
;Two nops are needed
;
;Disable self-refresh, DRAM ignored, one wait is
;selected
;Select 4MB and one wait
;Inhibit instruction to access DRAM area
25. DRAM Controller
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