MC908GR48AMFAE Freescale Semiconductor, MC908GR48AMFAE Datasheet - Page 91
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MC908GR48AMFAE
Manufacturer Part Number
MC908GR48AMFAE
Description
IC MCU 8BIT 48K FLASH 48-LQFP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908GR32ACFJE.pdf
(314 pages)
Specifications of MC908GR48AMFAE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI, SPI
Peripherals
LVD, POR, PWM
Number Of I /o
37
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC908GR48AMFAE
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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COPRS — COP Rate Select Bit
LVISTOP — LVI Enable in Stop Mode Bit
LVIRSTD — LVI Reset Disable Bit
LVIPWRD — LVI Power Disable Bit
LVI5OR3 — LVI 5-V or 3-V Operating Mode Bit
SSREC — Short Stop Recovery Bit
Freescale Semiconductor
COPRS selects the COP timeout period. Reset clears COPRS. See
Properly (COP) Module
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the LVI to operate during stop mode.
Reset clears LVISTOP.
LVIRSTD disables the reset signal from the LVI module. See
LVIPWRD disables the LVI module. See
LVI5OR3 selects the voltage operating mode of the LVI module (see
(LVI)). The voltage mode selected for the LVI should match the operating V
Electrical
SSREC enables the CPU to exit stop mode with a delay of 32 CGMXCLK cycles instead of a
4096-CGMXCLK cycle delay.
1 = COP timeout period = 8176 CGMXCLK cycles
0 = COP timeout period = 262,128 CGMXCLK cycles
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
1 = LVI module resets disabled
0 = LVI module resets enabled
1 = LVI module power disabled
0 = LVI module power enabled
1 = LVI operates in 5-V mode
0 = LVI operates in 3-V mode
1 = Stop mode recovery after 32 CGMXCLK cycles
0 = Stop mode recovery after 4096 CGMXCLK cycles
Note: LVI5OR3 is only reset via POR (power-on reset).
Specifications) for the LVI’s voltage trip points for each of the modes.
Address:
The LVI5OR3 bit is cleared by a power-on reset (POR) only. Other resets
will leave this bit unaffected.
Exiting stop mode by any reset will result in the long stop recovery.
Reset:
Read:
Write:
MC68HC908GR60A • MC68HC908GR48A • MC68HC908GR32A Data Sheet, Rev. 5
COPRS
$001F
Bit 7
0
Figure 5-2. Configuration Register 1 (CONFIG1)
LVISTOP
6
0
LVIRSTD
5
0
Chapter 11 Low-Voltage Inhibit
LVIPWRD
NOTE
NOTE
4
0
LVI5OR3
See note
3
Chapter 11 Low-Voltage Inhibit
SSREC
2
0
Chapter 6 Computer Operating
Chapter 11 Low-Voltage Inhibit
(LVI).
STOP
1
0
DD
(see
Functional Description
COPD
Bit 0
Chapter 20
0
(LVI).
91
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